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參數(shù)資料
| 型號(hào)： | ADS1252U |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24-BIT SER 41.7KHZ 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 視頻文件： | Nuts and Bolts of the Delta-Sigma Converter |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 41.7k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 40mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁面： | 889 (CN2011-ZH PDF) |
| 配用： | 296-19906-ND - EVAL MOD FOR ADS1252 |
ADS1252
11
SBAS127D
www.ti.com
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
56
57
58
59
60
61
62
63
64
65
55
Frequency (Hz)
Gain
(dB)
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
56
57
58
59
60
61
62
63
64
65
55
Frequency (Hz)
Gain
(dB)
FIGURE 9. Expanded Digital Filter Response (60Hz with a
60Hz Notch).
FIGURE 10. Expanded Digital Filter Response (60Hz with a
10Hz Notch).
to the DOR from MSB to LSB in the time defined by t1 (see
Figures 11 and 12). The DOUT/DRDY line then drives the
line LOW for the time defined by t2, and then drives the line
HIGH for the time defined by t3 to indicate that new data is
available to be read. At this point, the function of the DOUT/
DRDY pin changes to DOUT mode, and data is shifted out
on the pin after t7. If the MSB is high (because of a negative
result) the DOUT/DRDY signal will stay HIGH after the end
of time t3. The device communicating with the ADS1252 can
provide SCLKs to the ADS1252 after the time defined by t6.
The normal mode of reading data from the ADS1252 is for
the device reading the ADS1252 to latch the data on the
rising edge of SCLK (since data is shifted out of the ADS1252
on the falling edge of SCLK). In order to retrieve valid data,
the entire DOR must be read before the DOUT/DRDY pin
reverts back to DRDY mode.
If SCLKs are not provided to the ADS1252 during the DOUT
mode, the MSB of the DOR is present on the DOUT/DRDY
line until the beginning of the time defined by t4. If an
incomplete read of the ADS1252 takes place in DOUT mode
(that is, fewer than 24 SCLKs are provided), the state of the
last bit read is present on the DOUT/DRDY line until the
beginning of the time defined by t4. If more than 24 SCLKs
are provided during DOUT mode, the DOUT/DRDY line
stays LOW until the beginning of the time defined by t4.
The internal data pointer for shifting data out on
DOUT/DRDY is reset on the falling edge of the time defined
by t1 and t4. This ensures that the first bit of data shifted out
of the ADS1252 after DRDY mode is always the MSB of new
data.
SYNCHRONIZING MULTIPLE CONVERTERS
The normal state of SCLK is LOW; however, by holding SCLK
HIGH, multiple ADS1252s can be synchronized. This is ac-
complished by holding SCLK HIGH for at least four, but less
than 20, consecutive DOUT/DRDY cycles (see Figure 13).
After the ADS1252 circuitry detects that SCLK has been held
HIGH for four consecutive DOUT/DRDY cycles, the DOUT/
DRDY pin pulses LOW for 3 CLK cycles and then held HIGH,
and the modulator is held in a reset state. The modulator
is released from reset and synchronization occurs on the
falling edge of SCLK. It is important to note that prior
to synchronization, the DOUT/DRDY pulse of multiple
ADS1252s in the system can have a difference in timing up
to one DRDY period. Therefore, to ensure synchronization,
the SCLK must be held HIGH for at least five DRDY cycles.
The first DOUT/DRDY pulse after the falling edge of
SCLK occurs at t14. Valid data is not present until the sixth
DOUT/DRDY pulse.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1252U | 制造商:Texas Instruments 功能描述:IC 24BIT ADC 41.7KSPS SMD |
| ADS1252U/2K5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1252U/2K5G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1252UG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24-Bit 40kHz RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1253 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER |
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