參數(shù)資料
型號: ADS1251
廠商: Texas Instruments, Inc.
英文描述: "ResolutionPlus 24-Bit
中文描述: ResolutionPlus 24 位 20kHz 低功耗模數(shù)轉(zhuǎn)換器
文件頁數(shù): 4/17頁
文件大?。?/td> 323K
代理商: ADS1251
ADS1251
12
SBAS184A
www.ti.com
POWER-DOWN MODE
The normal state of SCLK is LOW; however, by holding
SCLK HIGH, the ADS1251 will enter power-down mode. This
is accomplished by holding SCLK HIGH for at least 20
consecutive DOUT/DRDY periods (see Figure 14). After the
ADS1251 circuitry detects that SCLK has been held HIGH for
four consecutive DOUT/DRDY cycles, the DOUT/DRDY pin
pulses LOW for one CLK cycle and then is held HIGH, and
the modulator is held in a reset state. If SCLK is held HIGH
for an additional 16 DOUT/DRDY periods, the ADS1251
enters power-down mode. The part will be released from
power-down mode on the falling edge of SCLK. It is impor-
tant to note that the DOUT/DRDY pin is held HIGH after four
DOUT/DRDY cycles, but power-down mode is not entered
for an additional 16 DOUT/DRDY periods. The first
DOUT/DRDY pulse after the falling edge of SCLK occurs at
t16 and indicates valid data. Subsequent DOUT/DRDY pulses
will occur normally.
SERIAL INTERFACE
The ADS1251 includes a simple serial interface which can be
connected to microcontrollers and digital signal processors in
a variety of ways. Communications with the ADS1251 can
commence on the first detection of the DOUT/DRDY pulse
after power up.
It is important to note that the data from the ADS1251 is a
24-bit result transmitted MSB-first in Offset Binary Two’s
Complement format, as shown in Table III.
The data must be clocked out before the ADS1251 enters
DRDY mode to ensure reception of valid data, as described
in the DOUT/DRDY section of this data sheet.
TABLE III. ADS1251 Data Format (Offset Binary Two’s
Complement).
DIFFERENTIAL VOLTAGE INPUT
DIGITAL OUTPUT (HEX)
+Full-Scale
7FFFFFH
Zero
000000H
–Full-Scale
800000H
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tDRDY
Conversion Cycle
384 CLK
ns
DRDY Mode
36 CLK
ns
DOUT Mode
348 CLK
ns
t1
DOR Write Time
6 CLK
ns
t2
DOUT/DRDY LOW Time
6 CLK
ns
t3
DOUT/DRDY HIGH Time (Prior to Data Out)
6 CLK
ns
t4
DOUT/DRDY HIGH Time (Prior to Data Ready)
24 CLK
ns
t5
Rising Edge of CLK to Falling Edge of DOUT/DRDY
30
ns
t6
End of DRDY Mode to Rising Edge of First SCLK
30
ns
t7
End of DRDY Mode to Data Valid (Propagation Delay)
30
ns
t8
Falling Edge of SCLK to Data Valid (Hold Time)
5
ns
t9
Falling Edge of SCLK to Next Data Out Valid (Propagation Delay)
30
ns
t10
SCLK Setup Time for Synchronization or Power Down
30
ns
t11
DOUT/DRDY Pulse for Synchronization or Power Down
1 CLK
ns
t12
Rising Edge of SCLK Until Start of Synchronization
1537 CLK
7679 CLK
ns
t13
Synchronization Time
0.5 CLK
6143.5 CLK
ns
t14
Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode
2042.5 CLK
ns
t15
Rising Edge of SCLK Until Start of Power Down
7681 CLK
ns
t16
Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode
2318.5 CLK
ns
t17
Falling Edge of Last DOUT/DRDY to Start of Power Down
6144.5 CLK
ns
TABLE II. Digital Timing.
FIGURE 11. DOUT/DRDY Partitioning.
DATA
DRDY Mode
DOUT Mode
DATA
t
4
t
2
t
3
t
1
DRDY Mode
DOUT/DRDY
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