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參數(shù)資料
| 型號(hào)： | ADS1251 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | "ResolutionPlus 24-Bit |
| 中文描述： | ResolutionPlus 24 位 20kHz 低功耗模數(shù)轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 323K |
| 代理商： | ADS1251 |
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ADS1251
11
SBAS184A
www.ti.com
is HIGH prior to the internal transfer of new data to the DOR.
The result of the A/D conversion is written to the DOR from
the Most Significant Bit (MSB) to the Least Significant Bit
(LSB) in the time defined by t1 (see Figures 11 and 12). The
DOUT/DRDY line then pulses LOW for the time defined by
t2, and then pulses HIGH for the time defined by t3 to indicate
that new data is available to be read. At this point, the
function of the DOUT/DRDY pin changes to DOUT mode.
Data is shifted out on the pin after t7. The device communi-
cating with the ADS1251 can provide SCLKs to the ADS1251
after the time defined by t6. The normal mode of reading data
from the ADS1251 is for the device reading the ADS1251 to
latch the data on the rising edge of SCLK (because data is
shifted out of the ADS1251 on the falling edge of SCLK). In
order to retrieve valid data, the entire DOR must be read
before the DOUT/DRDY pin reverts back to DRDY mode.
If SCLKs are not provided to the ADS1251 during the DOUT
mode, the MSB of the DOR is present on the DOUT/DRDY
line until the time defined by t4. If an incomplete read of the
ADS1251 takes place while in DOUT mode (that is, less than
24 SCLKs were provided), the state of the last bit read is
present on the DOUT/DRDY line until the time defined by t4.
If more than 24 SCLKs are provided during DOUT mode, the
DOUT/DRDY line stays LOW until the time defined by t4.
The internal data pointer for shifting data out on DOUT/DRDY
is reset on the falling edge of the time defined by t1 and t4.
This ensures that the first bit of data shifted out of the
ADS1251 after DRDY mode is always the MSB of new data.
SYNCHRONIZING MULTIPLE CONVERTERS
The normal state of SCLK is LOW; however, by holding SCLK
HIGH, multiple ADS1251s can be synchronized. This is accom-
plished by holding SCLK HIGH for at least four, but less than 20,
consecutive DOUT/DRDY cycles (see Figure 13). After the
ADS1251 circuitry detects that SCLK has been held HIGH for
four consecutive DOUT/DRDY cycles, the DOUT/DRDY pin
pulses LOW for one CLK cycle and then is held HIGH, and the
modulator is held in a reset state. The modulator will be
released from reset and synchronization occurs on the falling
edge of SCLK. With multiple converters, the falling edge tran-
sition of SCLK must occur simultaneously on all devices. It is
important to note that prior to synchronization, the DOUT/DRDY
pulse of multiple ADS1251s in the system could have a differ-
ence in timing up to one DRDY period. Therefore, to ensure
synchronization, the SCLK must be held HIGH for at least five
DRDY cycles. The first DOUT/DRDY pulse after the falling
edge of SCLK occurs at t14. The first DOUT/DRDY pulse
indicates valid data.
FIGURE 9. Expanded Digital Filter Response (60Hz with a
60Hz data output rate).
FIGURE 10. Expanded Digital Filter Response (60Hz with a
10Hz data output rate).
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
56
57
58
59
60
61
62
63
64
65
55
Frequency (Hz)
Gain
(dB)
DIGITAL FILTER RESPONSE
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
56
57
58
59
60
61
62
63
64
65
55
Frequency (Hz)
Gain
(dB)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS5102IPFBR | 1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE |
| ADS5103 | "10 Bit |
| ADS5103CPFB | 1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE |
| ADS5103CPFBR | 1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE |
| ADS5103EVM | 1.8-V ANALOG SUPPLY, 10-BIT, 65/40 MSPS ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1251EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1251 ADC Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS1251U | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24Bit 20kHz Lo-Power RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1251U | 制造商:Texas Instruments 功能描述:IC 24BIT ADC SMD 1251 SOIC8 |
| ADS1251U | 制造商:Texas Instruments 功能描述:IC ADC 24BIT 20KSPS SOIC-8 |
| ADS1251U/2K5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ResolutionPlus 24Bit 20kHz Lo-Power RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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