ACR (Address 02H) Analog Control Register <" />
參數資料
型號： ADS1241MEVM
廠商： Texas Instruments
文件頁數： 8/30頁
文件大?。?/td> 0K
描述： EVALUATION MODULE FOR ADS1241M
產品培訓模塊： Data Converter Basics
視頻文件： Nuts and Bolts of the Delta-Sigma Converter
標準包裝： 1
ADC 的數量： 1
位數： 24
采樣率（每秒）： 15
數據接口： SPI?
輸入范圍： 0 ~ 2.5 V
在以下條件下的電源（標準）： 0.6mW @ 3V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： ADS1241M
已供物品： 板
產品目錄頁面： 889 (CN2011-ZH PDF)
相關產品： ADS1241EG4-ND - IC ADC 24-BIT SER PROGBL 28-SSOP
ADS1241E/1KG4-ND - IC ADC 24-BIT SER PROGBL 28-SSOP
296-25895-2-ND - IC ADC 24-BIT SER PROGBL 28-SSOP
ADS1241E-ND - IC ADC 24-BIT SER PROGBL 28-SSOP
其它名稱： 296-18358
ADS1240, 1241
16
SBAS173F
www.ti.com
ACR (Address 02H) Analog Control Register
Reset Value = X0H
bit 7
DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
bit 6
U/B: Data Format
0 = Bipolar (default)
1 = Unipolar
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DRDY
U/B
SPEED
BUFEN
BIT ORDER RANGE
DR1
DR0
U/B
ANALOG INPUT
DIGITAL OUTPUT (Hex)
+FSR
0x7FFFFF
0
Zero
0x000000
–FSR
0x800000
+FSR
0xFFFFFF
1
Zero
0x000000
–FSR
0x000000
bit 5
SPEED: Modulator Clock Speed
0 = fMOD = fOSC/128 (default)
1 = fMOD = fOSC/256
bit 4
BUFEN: Buffer Enable
0 = Buffer Disabled (default)
1 = Buffer Enabled
bit 3
BIT ORDER: Data Output Bit Order
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
This configuration bit controls only the bit order
within the byte of data that is shifted out. Data is
always shifted out of the part most significant byte
first. Data is always shifted into the part most
significant bit first.
bit 2
RANGE: Range Select
0 = Full-Scale Input Range equal to
±V
REF
(default).
1 = Full-Scale Input Range equal to
±1/2 V
REF
NOTE: This allows reference voltages as high as
AVDD, but even with a 5V reference voltage the
calibration must be performed with this bit set to 0.
bit 1-0
DR1: DR0: Data Rate
(fOSC = 2.4576MHz, SPEED = 0)
00 = 15Hz (default)
01 = 7.5Hz
10 = 3.75Hz
11 = Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SIGN
OSET6
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIO 7
DIO 6
DIO 5
DIO 4
DIO 3
DIO 2
DIO 1
DIO 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
ODAC (Address 03 ) Offset DAC
Reset Value = 00H
bit 7
Sign
0 = Positive
1 = Negative
Offset
V
2 PGA
OSET [6 : 0]
127
RANGE
0
REF
=
=
Offset
V
PGA
OSET
RANGE
REF
=
=
4
60
127
1
[: ]
NOTE: The offset DAC must be enabled after calibration or the calibration
nullifies the effects.
DIO (Address 04H) Data I/O
Reset Value = 00H
If the IOCON register is configured for data, a value written
to this register appears on the data I/O pins if the pin is
configured as an output in the DIR register. Reading this
register returns the value of the data I/O pins.
Bit 4 to bit 7 is not used in ADS1240.
DIR (Address 05H) Direction Control for Data I/O
Reset Value = FFH
Each bit controls whether the corresponding data I/O pin is
an output (= 0) or input (= 1). The default power-up state is
as inputs.
Bit 4 to bit 7 is not used in ADS1240.
IOCON (Address 06H) I/O Configuration Register
Reset Value = 00H
bit 7-0
IO7: IO0: Data I/O Configuration
0 = Analog (default)
1 = Data
Configuring the pin as a data I/O pin allows it to be controlled
through the DIO and DIR registers.
Bit 4 to bit 7 is not used in ADS1240.
OCR0 (Address 07H) Offset Calibration Coefficient
(Least Significant Byte)
Reset Value = 00H
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