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參數(shù)資料
| 型號： | ADS1241MEVM |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 3/30頁 |
| 文件大小： | 0K |
| 描述： | EVALUATION MODULE FOR ADS1241M |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 視頻文件： | Nuts and Bolts of the Delta-Sigma Converter |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | SPI? |
| 輸入范圍： | 0 ~ 2.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 0.6mW @ 3V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | ADS1241M |
| 已供物品： | 板 |
| 產(chǎn)品目錄頁面： | 889 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | ADS1241EG4-ND - IC ADC 24-BIT SER PROGBL 28-SSOP ADS1241E/1KG4-ND - IC ADC 24-BIT SER PROGBL 28-SSOP 296-25895-2-ND - IC ADC 24-BIT SER PROGBL 28-SSOP ADS1241E-ND - IC ADC 24-BIT SER PROGBL 28-SSOP |
| 其它名稱： | 296-18358 |
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ADS1240, 1241
11
SBAS173F
www.ti.com
Figure 4 shows a short-circuited sensor. Since the inputs are
shorted and at the same potential, the ADS1240/41 signal
outputs are approximately zero. (Note that the code for
shorted inputs is not exactly zero due to internal series
resistance, low-level noise and other error sources.)
The buffer draws additional current when activated. The
current required by the buffer depends on the PGA setting.
When the PGA is set to 1, the buffer uses approximately
50
A; when the PGA is set to 128, the buffer uses approxi-
mately 500
A.
PGA
The Programmable Gain Amplifier (PGA) can be set to gains
of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the
effective resolution of the A/D converter. For instance, with a
PGA of 1 on a 5V full-scale signal, the A/D converter can
resolve down to 1
V. With a PGA of 128 and a full-scale signal
of 39mV, the A/D converter can resolve down to 75nV. AVDD
current increases with PGA settings higher than 4.
OFFSET DAC
The input to the PGA can be shifted by half the full-scale input
range of the PGA using the Offset DAC (ODAC) register. The
ODAC register is an 8-bit value; the MSB is the sign and the
seven LSBs provide the magnitude of the offset. Using the
offset DAC does not reduce the performance of the A/D
converter. For more details on the ODAC, please refer to TI
application report SBAA077.
MODULATOR
The modulator is a single-loop second-order system. The
modulator runs at a clock speed (fMOD) that is derived from
the external clock (fOSC). The frequency division is deter-
mined by the SPEED bit in the SETUP register, as shown in
Table I.
OPEN CIRCUIT
AV
DD
AV
DD
0V
2
A
2
A
CODE = 0x7FFFFF
H
ADC
FIGURE 3. Burnout detection while sensor is open-circuited.
SHORT
CIRCUIT
AV
DD
AV
DD/2
AV
DD/2
2
A
2
A
CODE
0
ADC
FIGURE 4. Burnout detection while sensor is short-circuited.
INPUT BUFFER
The input impedance of the ADS1240/41 without the buffer
enabled is approximately 5M
/PGA. For systems requiring
very high input impedance, the ADS1240/41 provides a
chopper-stabilized differential FET-input voltage buffer. When
activated, the buffer raises the ADS1240/41 input impedance
to approximately 5G
.
The buffer’s input range is approximately 50mV to AVDD –
1.5V. The buffer’s linearity will degrade beyond this range.
Differential signals should be adjusted so that both signals
are within the buffer’s input range.
The buffer can be enabled using the BUFEN pin or the
BUFEN bit in the ACR register. The buffer is on when the
BUFEN pin is high and the BUFEN bit is set to one. If the
BUFEN pin is low, the buffer is disabled. If the BUFEN bit is
set to zero, the buffer is also disabled.
SPEED
DR BITS
1st NOTCH
fOSC
BIT
fMOD
00
01
10
FREQ.
2.4576MHz
0
19,200Hz
15Hz
7.5Hz
3.75Hz
50/60Hz
1
9,600Hz
7.5Hz
3.75Hz 1.875Hz
25/30Hz
4.9152MHz
0
38,400Hz
30Hz
15Hz
7.5Hz
100/120Hz
1
19,200Hz
15Hz
7.5Hz
3.75Hz
50/60Hz
TABLE I. Output Configuration.
CALIBRATION
The offset and gain errors can be minimized with calibration.
The ADS1240 and ADS1241 support both self and system
calibration.
Self-calibration of the ADS1240 and ADS1241 corrects inter-
nal offset and gain errors and is handled by three commands:
SELFCAL, SELFGAL, and SLEFOCAL. The SELFCAL com-
mand performs both an offset and gain calibration. SELFGCAL
performs a gain calibration and SELFOCAL performs an
offset calibration, each of which takes two tDATA periods to
complete. During self-calibration, the ADC inputs are discon-
nected internally from the input pins. The PGA must be set to
1 prior to issuing a SELFCAL or SELFGCAL command. Any
PGA is allowed when issuing a SELFOCAL command. For
example, if using PGA = 64, first set PGA = 1 and issue
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