t1 SCLK Period 4t
參數(shù)資料
型號: ADS1241MEVM
廠商: Texas Instruments
文件頁數(shù): 27/30頁
文件大?。?/td> 0K
描述: EVALUATION MODULE FOR ADS1241M
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
視頻文件: Nuts and Bolts of the Delta-Sigma Converter
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 24
采樣率(每秒): 15
數(shù)據(jù)接口: SPI?
輸入范圍: 0 ~ 2.5 V
在以下條件下的電源(標(biāo)準(zhǔn)): 0.6mW @ 3V
工作溫度: -40°C ~ 85°C
已用 IC / 零件: ADS1241M
已供物品:
產(chǎn)品目錄頁面: 889 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: ADS1241EG4-ND - IC ADC 24-BIT SER PROGBL 28-SSOP
ADS1241E/1KG4-ND - IC ADC 24-BIT SER PROGBL 28-SSOP
296-25895-2-ND - IC ADC 24-BIT SER PROGBL 28-SSOP
ADS1241E-ND - IC ADC 24-BIT SER PROGBL 28-SSOP
其它名稱: 296-18358
ADS1240, 1241
6
SBAS173F
www.ti.com
SPEC
DESCRIPTION
MIN
MAX
UNITS
t1
SCLK Period
4tOSC Periods
3
DRDY Periods
t2
SCLK Pulse Width, HIGH and LOW
200
ns
t3
CS low to first SCLK Edge; Setup Time(2)
0ns
t4
DIN Valid to SCLK Edge; Setup Time
50
ns
t5
Valid DIN to SCLK Edge; Hold Time
50
ns
t6
Delay between last SCLK edge for DIN and first SCLK edge for DOUT:
RDATA, RDATAC, RREG, WREG
50
tOSC Periods
t7(1)
SCLK Edge to Valid New DOUT
50
ns
t8(1)
SCLK Edge to DOUT, Hold Time
0
ns
t9
Last SCLK Edge to DOUT Tri-State
6
10
tOSC Periods
NOTE: DOUT goes tri-state immediately when CS goes HIGH.
t10
CS LOW time after final SCLK edge.
Read from the device
0
tOSC Periods
Write to the device
8
tOSC Periods
t11
Final SCLK edge of one command until first edge SCLK
of next command:
RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC
4tOSC Periods
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL
2
DRDY Periods
SELFCAL
4
DRDY Periods
RESET (also SCLK Reset or RESET Pin)
16
tOSC Periods
t16
Pulse Width
4tOSC Periods
t17
Allowed analog input change for next valid conversion.
5000
tOSC Periods
t18
DOR update, DOR data not valid.
4
tOSC Periods
t19
First SCLK after DRDY goes LOW:
RDATAC Mode
10
tOSC Periods
Any other mode
0
tOSC Periods
NOTES: (1) Load = 20pF
10k to DGND.
(2) CS may be tied LOW.
TIMING DIAGRAMS
TIMING CHARACTERISTICS TABLE
t
4
MSB
(Command or Command and Data)
LSB
t
5
t
1
t
3
CS
SCLK
(POL = 0)
D
IN
D
OUT
NOTE: (1) Bit order = 0.
SCLK Reset Waveform
t
7
MSB(1)
LSB(1)
t
8
t
10
t
2
t
2
t
11
t
6
t
9
SCLK
(POL = 1)
t
12
t
14
t
15
t
13
t
13
SCLK
ADS1240 or ADS1241
Resets On
Falling Edge
300 t
OSC < t12 < 500 tOSC
t
13 : > 5 tOSC
550 t
OSC < t14 < 750 tOSC
1050 t
OSC < t15 < 1250 tOSC
DIAGRAM 1.
DIAGRAM 2.
t
17
t
18
DRDY
SCLK
t
DATA
t
16
RESET, DSYNC, PDWN
t
19
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