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參數(shù)資料
| 型號(hào)： | ADS1191IPBS |
| 廠商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 27/67頁(yè) |
| 文件大小： | 0K |
| 描述： | IC AFE 16BIT 8KSPS 1CH 32TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 1 |
| 電壓 - 電源，模擬： | 2.7 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 1.7 V ~ 3.6 V |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（5x5） |
| 包裝： | 管件 |
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START
DRDY
CS
SCLK
DIN
DOUT
Hi-Z
RDATACOpcode
StatusRegister+2-ChannelData
NextData
t
UPDATE
(1)
SBAS566A – DECEMBER 2011 – REVISED SEPTEMBER 2012
START: Start Conversions
This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions
are in progress this command has no effect. The STOP opcode command is used to stop conversions. If the
START command is immediately followed by a STOP command then have a gap of 4 tCLK cycles between them.
When the START opcode is sent to the device, keep the START pin low until the STOP command is issued.
(See the START subsection of the SPI Interface section for more details.) There are no restrictions on the
SCLK rate for this command and it can be issued any time.
STOP: Stop Conversions
This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP
command is sent, the conversion in progress completes and further conversions are stopped. If conversions are
already stopped, this command has no effect. There are no restrictions on the SCLK rate for this command and it
can be issued any time.
OFFSETCAL: Channel Offset Calibration
This command is used to cancel the channel offset. The CALIB_ON bit in the MISC2 register must be set to '1'
before issuing this command. OFFSETCAL must be executed every time there is a change in the PGA gain
settings.
RDATAC: Read Data Continuous
This opcode enables the output of conversion data on each DRDY without the need to issue subsequent read
data opcodes. This mode places the conversion data in the output register and may be shifted out directly. The
read data continuous mode is the default mode of the device and the device defaults in this mode on power-up.
RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, an
SDATAC command must be issued before any other commands can be sent to the device. There is no
restriction on the SCLK rate for this command. However, the subsequent data retrieval SCLKs or the SDATAC
opcode command should wait at least 4 tCLK cycles. The timing for RDATAC is shown in Figure 38. As Figure 38
shows, there is a keep out zone of 4 tCLK cycles around the DRDY pulse where this command cannot be issued
in. If no data are retrieved from the device, DOUT and DRDY behave similarly in this mode. To retrieve data from
the device after the RDATAC command is issued, make sure either the START pin is high or the START
command is issued. Figure 38 shows the recommended way to use the RDATAC command. RDATAC is ideally
suited for applications such as data loggers or recorders where registers are set once and do not need to be re-
configured.
(1)
tUPDATE = 4 * tCLK. Do not read data during this time.
Figure 38. RDATAC Usage
Copyright 2011–2012, Texas Instruments Incorporated
33
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