參數(shù)資料
型號: ADP5042ACPZ-2-R7
廠商: Analog Devices Inc
文件頁數(shù): 23/32頁
文件大?。?/td> 1378K
描述: IC REG TRPL BCK/LINEAR 20LFCSP
標(biāo)準(zhǔn)包裝: 1
拓?fù)洌?/td> 降壓(降壓)同步(1),線性(LDO)(2)
功能: 任何功能
輸出數(shù): 3
頻率 - 開關(guān): 3MHz
電壓/電流 - 輸出 1: 1.5V,800mA
電壓/電流 - 輸出 2: 1.8V,300mA
電壓/電流 - 輸出 3: 3.3V,300mA
帶 LED 驅(qū)動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 1.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 20-LFCSP-WQ(4x4)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ADP5042ACPZ-2-R7DKR
Data Sheet
ADP5042
 
Rev. A | Page 23 of 32
APPLICATIONS INFORMATION
BUCK EXTERNAL COMPONENT SELECTION
Trade-offs between performance parameters such as efficiency
and transient response can be made by varying the choice of
external components in the applications circuit, as shown in
Figure 66.
Inductor
The high switching frequency of the ADP5042 buck allows for
the selection of small chip inductors. For best performance, use
inductor values between 0.7 糎 and 3 糎. Suggested inductors
are shown in Table 11.
The peak-to-peak inductor current ripple is calculated using
the following equation:
L
f
V
V
V
V
I
SW
IN
OUT
IN
OUT
RIPPLE
?/DIV>
?/DIV>

?/DIV>
=
)
(
 
where:
f
SW
 is the switching frequency.
L is the inductor value.
The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current is
calculated using the following equation:
2
)
(
RIPPLE
MAX
LOAD
PEAK
I
I
I
+
=
 
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal dc
resistance (DCR). Larger sized inductors have smaller DCR,
which may decrease inductor conduction losses. Inductor core
losses are related to the magnetic permeability of the core material.
Because the buck is high switching frequency dc-to-dc converters,
shielded ferrite core material is recommended for its low core
losses and low EMI.
Table 11. Suggested 1.0 糎 Inductors
Vendor
Model
Dimensions
(mm)
ISAT
(mA)
DCR
(m?
Murata
LQM2MPN1R0NG0B    2.0 ?1.6 ?0.9
1400
85
Murata
LQM18FN1R0M00B    1.6 ?0.8 ?0.8
150
26
Taiyo Yuden    CBMF1608T1R0M
1.6 ?0.8 ?0.8     290
90
Coilcraft
EPL2014-102ML
2.0 ?2.0 ?1.4
900
59
TDK
GLFR1608T1R0M-LR    1.6 ?0.8 ?0.8     230
80
Coilcraft
0603LS-102
1.8 ?1.69 ?1.1    400
81
Toko
MDT2520-CN
2.5 ?2.0 ?1.2
1350
85
 
Output Capacitor
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
output voltage dc bias.
Ceramic capacitors are manufactured with a variety of dielec-
trics, each with a different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R
dielectrics with a voltage rating of 6.3 V or 10 V are recom-
mended for best performance. Y5V and Z5U dielectrics are
not recommended for use with any dc-to-dc converter because
of their poor temperature and dc bias characteristics.
The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calcu-
lated using the following equation:
C
EFF = COUT ?/SPAN> (1  TEMPCO) ?/SPAN> (1  TOL) 
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over 40癈 to +85癈 is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
COUT is 9.2481 糉 at 1.8 V, as shown in Figure 61.
Substituting these values in the equation yields
CEFF = 9.2481 糉 ?(1  0.15) ?(1  0.1) = 7.0747 糉
To guarantee the performance of the buck, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
0
2
4
6
8
10
12
0
1
2
3
4
5
6
DC BIAS VOLTAGE  V
 
Figure 61. Typical Capacitor Performance
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