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參數(shù)資料
| 型號： | ADP5024ACPZ-1-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, PQCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, MO-220, LCC-24 |
| 文件頁數(shù)： | 16/27頁 |
| 文件大?。?/td> | 926K |
| 代理商： | ADP5024ACPZ-1-R7 |
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Preliminary Technical Data
ADP5024
Rev. PrA | Page 23 of 27
LDO EXTERNAL COMPONENT SELECTION
Feedback Resistors
For the adjustable model, the maximum value of Rb is not to
exceed 200 k (see Figure 48).
Output Capacitor
The ADP5024 LDO is designed for operation with small, space-
saving ceramic capacitors, but functions with most
commonly used capacitors as long as care is taken with the
ESR value. The ESR of the output capacitor affects stability of
the LDO control loop. A minimum of 0.70 F capacitance
with an ESR of 1 or less is recommended to ensure stability of
the ADP5024. Transient response to changes in load current is
also affected by output capacitance. Using a larger value of
output capacitance improves the transient response of the
ADP5024 to large changes in load current.
Input Bypass Capacitor
Connecting a 1 F capacitor from VIN3 to ground reduces
the circuit sensitivity to printed circuit board (PCB) layout,
especially when long input traces or high source impedance
are encountered. If greater than 1 F of output capacitance is
required, increase the input capacitor to match it.
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5024 as
long as they meet the minimum capacitance and maximum
ESR requirements. Ceramic capacitors are manufactured with a
variety of dielectrics, each with a different behavior over
temperature and applied voltage. Capacitors must have a
dielectric adequate to ensure the minimum capacitance over the
necessary temperature range and dc bias conditions. X5R or
X7R dielectrics with a voltage rating of 6.3 V or 10 V are
recommended for best performance. Y5V and Z5U dielectrics
are not recommended for use with any LDO because of their
poor temperature and dc bias characteristics.
Figure 51 depicts the capacitance vs. voltage bias
characteristic of a 0402 1 F, 10 V, X5R capacitor. The voltage
stability of a capacitor is strongly influenced by the capacitor
size and voltage rating. In general, a capacitor in a larger
package or higher voltage rating exhibits better stability. The
over the 40°C to +85°C temperature range and is not a
function of package or voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
0
1
2
3
4
5
6
DC BIAS VOLTAGE (V)
C
A
P
A
C
IT
A
N
C
E
(
F
)
0
9
7
0
3
-0
1
2
Figure 51. Capacitance vs. Voltage Characteristic
Use the following equation to determine the worst-case capa-
citance accounting for capacitor variation over temperature,
component tolerance, and voltage.
CEFF = CBIAS × (1 TEMPCO) × (1 TOL)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over 40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is
assumed to be 10% and CBIAS is 0.94 μF at 1.8 V as shown in
Figure 51.
Substituting these values into the following equation:
CEFF = 0.94 μF × (1 0.15) × (1 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP5024, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors are evaluated for each application.
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| ADP5024ACPZ-2-R7 | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
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