參數(shù)資料
型號(hào): ADP5024ACPZ-1-R7
廠商: ANALOG DEVICES INC
元件分類(lèi): 穩(wěn)壓器
英文描述: SWITCHING REGULATOR, PQCC24
封裝: 4 X 4 MM, ROHS COMPLIANT, MO-220, LCC-24
文件頁(yè)數(shù): 10/27頁(yè)
文件大?。?/td> 926K
代理商: ADP5024ACPZ-1-R7
ADP5024
Preliminary Technical Data
Rev. PrA | Page 18 of 27
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated in the system. If the input
voltage on VIN1 drops below a typical 2.15 V UVLO
threshold, all channels shut down. In the buck channels, both
the power switch and the synchronous rectifier turn off.
When the voltage on VIN1 rises above the UVLO threshold,
the part is enabled once more.
Alternatively, the user can select device models with a UVLO
set at a higher level, suitable for USB applications. For these
models, the device reaches the turn-off threshold when the
input supply drops to 3.65 V typical.
In case of a thermal or UVLO event, the active pull-downs (if
factory enabled) are enabled to discharge the output
capacitors quickly. The pull-downs remain engaged until the
input supply voltage or thermal fault event is no longer
present.
Enable/Shutdown
The ADP5024 has an individual control pin for each
regulator. A logic level high applied to the ENx pin activates a
regulator, whereas a logic level low turns off a regulator.
Figure 46 shows the regulator activation timings for the
ADP5024 when all enable pins are connected to AVIN. Also
shown is the active pull-down activation.
AVIN
VOUT3
VOUT1
VUVLO
30us (MIN)
50us (MIN)
VOUT2
VPOR
Buck1,LDO
Pull-Downs
Buck2
Pull-Down
30us (MIN)
50us (MIN)
Figure 46. Regulator Sequencing on ADP5024 (EN1 = EN2 = EN3 = VAVIN)
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