- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1899 > ADN2860ACPZ250-RL7 (Analog Devices Inc)IC POT DGTL 3CH 250K 24-LFCSP PDF資料下載
參數(shù)資料
| 型號： | ADN2860ACPZ250-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 0K |
| 描述： | IC POT DGTL 3CH 250K 24-LFCSP |
| 標準包裝： | 1 |
| 接片： | 128，512，512 |
| 電阻（歐姆）： | 250k |
| 電路數(shù)： | 3 |
| 溫度系數(shù)： | 標準值 35 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 標準包裝 |
| 其它名稱： | ADN2860ACPZ250RDKR |
ADN2860
Rev. B | Page 17 of 20
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at the A, B, and W terminals (Figure 30), it is important to
power VDD/VSS before applying voltage to the A, B, and W
terminals. Otherwise, the diode is forward biased such that
VDD/VSS are powered unintentionally, which affects the rest of
the circuit. The ideal power-up sequence is as follows: GND,
VDD, VSS, digital inputs, and VA/B/W. The order of powering VA,
VB, VW, and the digital inputs is not important, as long as they
are powered after VDD/VSS.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use compact, minimum-lead-
length layout design. Make the leads to the input as direct as
possible with a minimum conductor length. Make sure that
ground paths have low resistance and low inductance.
It is also a good practice to bypass the power supplies with
quality capacitors. Use low equivalent series resistance (ESR)
1 μF to 10 μF tantalum or electrolytic capacitors at the supplies
to minimize any transient disturbance and filter low frequency
ripple. Figure 31 illustrates the basic supply-bypassing
configuration for the ADN2860.
VDD
VSS
VDD
VSS
GND
ADN2860
C3
C4
C1
C2
+
10
μF
10
μF
0.1
μF
0.1
μF
03615-031
Figure 31. Power Supply Bypassing
Solder the slug on the bottom of the LFCSP package to a floating
pad to improve thermal dissipation. Do not connect the slug to
a ground plane on the PCB.
RDAC STRUCTURE
The patent pending RDAC contains a string of equal resistor
segments with an array of analog switches. The switches
together act as the wiper connection.
The ADN2860 has two RDACs with 512 connection points,
allowing it to provide better than 0.2% progammability
resolution. The ADN2860 also contains a third RDAC with
128-step resolution.
Figure 32 shows an equivalent structure of the connections
between the two terminals that make up one channel of an
RDAC. The SWB switch is always on, while one of switches
SW(0) to SW(2N 1) may or may not be on at any given time,
depending on the resistance position decoded from the data bits
in the RDAC register.
Since the switches are nonideal, there is a 100 Ω wiper resistance,
RW. Wiper resistance is a function of supply voltage and
temperature; lower supply voltages and higher temperatures
result in higher wiper resistances. Consideration of wiper
resistance dynamics is important in applications in which
accurate prediction of output resistance is required.
03615-032
RDAC
WIPER
REGISTER
AND
DECODER
DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY
RS = RAB/2N
RS
AX
WX
BX
SWB
SW(0)
SW(1)
SW(2N–1)
SW(2N–2)
SWA
Figure 32. Equivalent RDAC Structure
CALCULATING THE PROGRAMMABLE RESISTANCE
The nominal resistance of the RDAC between the A and B
terminals is available in 25 kΩ or 250 kΩ. The final two or three
digits of the part number determine the nominal resistance
value, for example, 25 kΩ = 25 and 250 kΩ = 250.
The following discussion describes the calculation of resistance
RWB(d) at different codes of a 25 kΩ part for RDAC0. The 9-bit
data-word in the RDAC latch is decoded to select one of the 512
possible settings.
The first wiper connection starts at the B terminal for data 0x000.
RWB(0) is 100 Ω of the wiper resistance and is independent of
the full-scale resistance. The second connection is the first tap
point where RWB(1) becomes 48.8 Ω + 100 = 148.8 Ω for data
0x001. The third connection is the next tap point representing
RWB(2) = 97.6 + 100 = 197.6 Ω for data 0x002, and so on. Each
LSB data-value increase moves the wiper up the resistor ladder
until the last tap point is reached at RWB(511) = 25,051 Ω. See
Figure 32 for a simplified diagram of the equivalent RDAC circuit.
These general equations determine the programmed output
resistance between terminals W and B.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADN4600ACPZ | IC CROSSPOINT SWITCH 8X8 64LFCSP |
| ADN4604ASVZ-RL | IC CROSSPOINT SWIT 16X16 100TQFP |
| ADN4605ABPZ | IC CROSSPOINT SWITCH 352BGA |
| ADN4661BRZ-REEL7 | IC DRIVER DIFF LVDS 1CH 8SOIC |
| ADN4662BRZ-REEL7 | IC RCVR DIFF LVDS 1CH 8SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADN2860ACPZ25-RL7 | 功能描述:IC POT DGTL 3CH 25K 24-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 標準包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標準值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| ADN2860-EVAL | 制造商:AD 制造商全稱:Analog Devices 功能描述:3-Channel Digital Potentiometer with Nonvolatile Memory |
| ADN2865 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC w/Loop Timed SERDES |
| ADN2865ACP | 制造商:AD 制造商全稱:Analog Devices 功能描述:Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC w/Loop Timed SERDES |
| ADN2865ACP-RL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC w/Loop Timed SERDES |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。