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參數(shù)資料
| 型號： | ADN2811ACP-CML |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | CLOCK RECOVERY CIRCUIT, QCC48 |
| 封裝： | 7 X 7 MM, LEAD FREE, MO-220-VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 359K |
| 代理商： | ADN2811ACP-CML |
REV. A
ADN2811
–7–
DEFINITION OF TERMS
Maximum, Minimum, and Typical Specifications
Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. Typical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the distribu-
tion. This procedure is intended to tolerate production variations.
If the mean shifts by 1.5 standard deviations, the remaining 4.5
standard deviations still provide a failure rate of only 3.4 parts
per million. For all tested parameters, the test limits are guardbanded
to account for tester variation to thus guarantee that no device is
shipped outside of data sheet specifications.
INPUT SENSITIVITY AND INPUT OVERDRIVE
Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the
logic output of the quantizer and the analog voltage input is
shown in Figure 4. For sufficiently large positive input voltage,
the output is always Logic 1; similarly for negative inputs, the
output is always Logic 0. However, the transitions between
output Logic Levels 1 and 0 are not at precisely defined input
voltage levels but occur over a range of input voltages. Within
this zone of confusion, the output may be either 1 or 0, or it
may even fail to attain a valid logic state. The width of this zone
is determined by the input voltage noise of the quantizer. The
center of the zone of confusion is the quantizer input offset
voltage. Input overdrive is the magnitude of signal required to
guarantee the correct logic level with 1
×
10
–10
confidence level.
0
1
INPUT (V p-p)
OUTPUT
NOISE
SENSITIVITY
(2 OVERDRIVE)
OFFSET
OVERDRIVE
Figure 4. Input Sensitivity and Input Overdrive
SINGLE-ENDED VS. DIFFERENTIAL
AC-coupling is typically used to drive the inputs to the quan-
tizer. The inputs are internally dc biased to a common-mode
potential of ~0.6 V. Driving the ADN2811 single-ended and
observing the quantizer input with an oscilloscope probe at the
point indicated in Figure 5 shows a binary signal with an average
value equal to the common-mode potential and instantaneous
values both above and below the average value. It is convenient
to measure the peak-to-peak amplitude of this signal and call
the minimum required value the quantizer sensitivity. Referring
to Figure 4, since both positive and negative offsets need to be
accommodated, the sensitivity is twice the overdrive.
50
50
QUANTIZER
+
ADN2811
VREF
PIN
SCOPE
PROBE
VREF
10mV p-p
Figure 5. Single-Ended Sensitivity Measurement
50
50
QUANTIZER
+
ADN2811
VREF
NIN
PIN
SCOPE
PROBE
VREF
5mV p-p
Figure 6. Differential Sensitivity Measurement
Driving the ADN2811 differentially (see Figure 6), sensitivity
seems to improve by observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a
single-ended probe. A 5 mV p–p signal appears to drive the
ADN2811 quantizer. However, the single-ended probe mea-
sures only half the signal. The true quantizer input signal is
twice this value since the other quantizer input is a complemen-
tary signal to the signal being observed.
LOS Response Time
The LOS response time is the delay between the removal of
the input signal and the indication of loss of signal (LOS) at
SDOUT. The LOS response time of the ADN2811 is 300 ns
typ when the inputs are dc-coupled. In practice, the time con-
stant of the ac-coupling at the quantizer input determines the
LOS response time.
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| ADN2811ACP-CML-RL | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R |
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| ADN2811ACPZ-CML-RL | 功能描述:IC CLK DATA REC SDH 2.66GHZ 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):上次購買時(shí)間 PLL:是 主要用途:SONET/SDH，STM 輸入:CML 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:是/是 頻率 - 最大值:2.66GHz 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商器件封裝:48-LFCSP（7x7） 標(biāo)準(zhǔn)包裝:1 |
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