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參數(shù)資料
| 型號： | ADN2811ACP-CML |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | CLOCK RECOVERY CIRCUIT, QCC48 |
| 封裝： | 7 X 7 MM, LEAD FREE, MO-220-VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 359K |
| 代理商： | ADN2811ACP-CML |
–12–
REV. A
ADN2811
APPLICATIONS INFORMATION
PCB Design Guidelines
Proper RF PCB design techniques must be used for optimal performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane to both analog and
digital grounds is recommended. The VEE pins should be sol-
dered directly to the ground plane to reduce series inductance.
If the ground plane is an internal plane and connections to the
ground plane are made through vias, multiple vias may be used
in parallel to reduce the series inductance, especially on Pins 33
and 34, which are the ground returns for the output buffers.
Use of a 10
μ
F electrolytic capacitor between VCC and GND is
recommended at the location where the 3.3 V supply enters the
PCB. Use of 0.1
μ
F and 1 nF ceramic chip capacitors should be
placed between IC power supply VCC and GND as close as
possible to the ADN2811 VCC pins. Again, if connections to the
supply and ground are made through vias, the use of multiple vias
in parallel will help to reduce series inductance, especially on Pins 35
and 36, which supply power to the high speed CLKOUTP/N and
DATAOUTP/N output buffers. Refer to the schematic in
Figure 17 for recommended connections.
Transmission Lines
Use of 50
transmission lines are required for all high fre-
quency input and output signals to minimize reflections,
including PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP,
and DATAOUTN (also REFCLKP, REFCLKN for a
155.2 MHz REFCLK). It is also recommended that the
PIN/NIN input traces are matched in length and that the
50
50
QUANTIZER
+
ADN2811
VREF
NIN
PIN
50
50
VCC
TDINP/N
LOOPEN
BYPASS
CDR
RETIMED
DATA
CLK
0
1
1
0
DATAOUTP/N
CLKOUTP/N SQUELCH
FROM
QUANTIZER
OUTPUT
Figure 16. Test Modes
CLKOUTP/N and DATAOUTP/N output traces are matched
in length. All high speed CML outputs, CLKOUTP/N and
DATAOUTP/N, also require 100
back termination chip
resistors connected between the output pin and VCC. These
resistors should be placed as close as possible to the output
pins. These 100
resistors are in parallel with on-chip 100
termination resistors to create a 50
back termination (see
Figure 18).
The high speed inputs, PIN and NIN, are internally terminated
with 50
to an internal reference voltage (see Figure 19). A 0.1
μ
F
capacitor is recommended between VREF, Pin 4, and GND to
provide an ac ground for the inputs.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
Soldering Guidelines for Chip-Scale Package
The lands on the 48-lead LFCSP are rectangular. The printed
circuit board pad for these should be 0.1 mm longer than the
package land length and 0.05 mm wider than the package land
width. The land should be centered on the pad. This will ensure
that the solder joint size is maximized. The bottom of the chip-
scale package has a central exposed pad. The pad on the printed
circuit board should be at least as large as this exposed pad.
The user must connect the exposed pad to analog VCC.
If vias are used, they should be incorporated into the pad at
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm and the via barrel should be plated with 1 oz.
copper to plug the via.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADN2811ACP-CML-RL | 制造商:Analog Devices 功能描述:CDR 2488.32Mbps/2666.06Mbps SONET/SDH 48-Pin LFCSP EP T/R |
| ADN2811ACPZ-CML | 功能描述:IC CLK/DATA REC W/AMP 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ADN2811ACPZ-CML-RL | 功能描述:IC CLK DATA REC SDH 2.66GHZ 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):上次購買時間 PLL:是 主要用途:SONET/SDH，STM 輸入:CML 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:是/是 頻率 - 最大值:2.66GHz 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商器件封裝:48-LFCSP（7x7） 標(biāo)準(zhǔn)包裝:1 |
| ADN2812 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2812ACP | 制造商:Analog Devices 功能描述:IC CLOCK/DATA RECOVERY |
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