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參數(shù)資料
| 型號(hào)： | ADMCF341 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DashDSP⑩ 28-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End |
| 中文描述： | DashDSP⑩28引腳閃存混合信號(hào)增強(qiáng)的DSP與模擬前端 |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 1106K |
| 代理商： | ADMCF341 |
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REV. 0
ADMCF341
–9–
PIN FUNCTION DESCRIPTION
The ADMCF341 is available in a 28-lead SOIC package.
Table I describes the pins.
Table I. Pin List
Pin Group
Name
No. of Input/
Pins
Output Function
RESET
SPORT1
1
1
2
I
I/O
Processor Reset Input
Serial Port 1 Pins (DT1/FL1,
DR1, SCLK1/SCLK0
2
)
Serial Port 0 Pins (DT0, DR0
TFSO, SCLK1/SCLK0
2
)
Processor Clock Output
External Clock or Quartz
Crystal Connection Point
Digital I/O Port Pins
SPORT0
1
5
I/O
CLKOUT
CLKIN, XTAL
1
1
2
I/O
I, O
PORTA0–
PORTA8
1
AUX0–AUX1
1
AH–CL
PWMTRIP
I
SENSE
1–
I
SENSE
3
VAUX0–VAUX2 3
I
CONST
9
I/O
2
6
1
3
O
O
I
I
Auxiliary PWM Outputs
PWM Outputs
PWM Trip Signal
I
SENSE
Inputs
I
O
Auxiliary Analog Inputs
ADC Constant Current
Source
Power Supply
Ground
1
V
DD
GND
1
1
I
I
NOTES
1
Multiplexed pins, individually selectable through PORTA_SELECT
and PORTA_DATA registers.
2
SCLK1/SCLK0 multiplexed signals. Selectable through MODECTRL
Register Bit 4.
INTERRUPT OVERVIEW
The ADMCF341 can respond to 18 different interrupt sources
with minimal overhead, seven of which are internal DSP core
interrupts and 11 from the motor control peripherals. The
seven DSP core interrupts are SPORT1 receive (or
IRQ0
) and
transmit (or
IRQ1
), SPORT0 receive and transmit, the internal
timer, and two software interrupts. The motor control periph-
eral interrupts are the nine programmable I/Os and two from
the PWM (PWMSYNC pulse and
PWMTRIP
). All motor
control interrupts are multiplexed into the DSP core through
the peripheral
IRQ2
interrupt. The interrupts are internally
prioritized and individually maskable. A detailed description of the
entire interrupt system of the ADMCF341 is presented later,
following a more detailed description of each peripheral block.
MEMORY MAP
The ADMCF341 has two distinct memory types: program and
data. In general, program memory contains user code and coef-
ficients, while the data memory is used to store variables and
data during program execution. Three kinds of program
memory are provided on the ADMCF341: RAM, ROM, and
FLASH. The motor control peripherals are memory mapped
into a region of the data memory space starting at 0x2000. The
complete program and data memory maps are given in Tables II
and III, respectively.
Table II. Program Memory Map
Memory
Type
Address Range
Function
0x0000–0x002F
0x0030–0x01FF
0x0200–0x07FF
0x0800–0x17FF
0x1800–0x1FFF
0x2000–0x20FF
RAM
RAM
Internal Vector Table
User Program Memory
Reserved
Reserved Program Memory
Reserved
User Program Memory
Sector 0
User Program Memory
Sector 1
User Program Memory
Sector 2
Reserved
ROM
FLASH
0x2100–0x21FF
FLASH
0x2200–0x2FFF
FLASH
0x3000–0x3FFF
Table III. Data Memory Map
Memory
Type
Address Range
Function
0x0000–0x1FFF
0x2000–0x20FF
0x2100–0x37FF
0x3800–0x39FF
0x3A00–0x3BFF
0x3C00–0x3FFF
Reserved
Memory Mapped Registers
Reserved
User Data Memory
Reserved
Memory Mapped Registers
RAM
RAM
FLASH MEMORY SUBSYSTEM
The ADMCF341 has 4K
nonvolatile flash memory. A flash programming utility is pro-
vided with the development tools, which perform the basic
device programming operations: erase, program, and verify.
The flash memory array is portioned into three asymmetrically
sized sectors of 256 words, 256 words, and 3584 words, labeled
sector 0, sector 1, and sector 2, respectively. These sectors are
mapped into external program memory address space.
Four flash memory interface registers are connected to the DSP.
These 16-bit registers are mapped into the register area of data
memory space. They are named flash memory control register
(FMCR), flash memory address register (FMAR), flash memory
data register low (FMDRL), and flash memory data register
high (FMDRH). These registers are diagrammed later in this
data sheet. They are used by the flash memory programming
utility. The user program may read these registers, but should
not modify them directly. The flash programming utility pro-
vides a complete interface to the flash memory.
It should be noted that the core accesses flash memory through
an external memory interface that multiplexes the program
memory and data memory buses into a single external bus.
Therefore, if more than one external transfer must be made in
the same instruction, there will be at least an overhead cycle
required.
24-bits of user-programmable,
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