參數(shù)資料
型號： ADMCF341
廠商： Analog Devices, Inc.
英文描述： DashDSP⑩ 28-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End
中文描述： DashDSP⑩28引腳閃存混合信號增強(qiáng)的DSP與模擬前端
文件頁數(shù)： 17/36頁
文件大小： 1106K
代理商： ADMCF341
REV. 0
ADMCF341
–17–
ADC Overview
The ADC of the ADMCF341 is based upon the single slope con-
version technique. This approach offers an inherently monotonic
conversion process within the noise and stability of its compo-
nents, and there will be no missing codes.
The single slope technique has been adopted on the
ADMCF341 for four channels that are simultaneously con-
verted. Refer to Figure 11 for the functional schematic of the
ADC. The main inputs (I
SENSE
1 to I
SENSE
3) are connected to
the ADC converter through three front end blocks. Figure 15
shows the block diagram of a single front end block. Each front
end block has a bipolar current amplifier (gain = –2.5) designed
to acquire the voltage on a current-sensing resistor, whose volt-
age can be either positive or negative with respect to the power
supply ground rail.
The fourth channel has been configured with a serially con-
nected 4-to-1 multiplexer. Table VI shows the multiplexer input
selection codes. One of these auxiliary multiplexed channels is
used to acquire the internal voltage reference (V
REF
) for calibra-
tion purposes.
Table VI. ADC Auxiliary Channel Selection
MODECTRL (1)
ADCMUX1
MODECTRL (0)
ADCMUX0
Select
VAUX0
VAUX1
VAUX2
Calibration (V
REF
)
0
0
1
1
0
1
0
1
ADC1
ADC2
ADC3
ADCAUX
COMP
I
SENSE
1
I
SENSE
2
I
SENSE
3
VAUX0
VAUX1
VAUX2
V
REF
I
CONST
CURRENT
VOLTAGE
CHANNEL1
CURRENT
VOLTAGE
CHANNEL2
CURRENT
VOLTAGE
CHANNEL3
4-1
MULTIPLEXER
VAUX0 (V)
VAUX1 (V)
VAUX2 (V)
VAUX3 (V)
MODECTRL REG <0..1>
COMP
COMP
COMP
I
CONST
FILTER
1
V1L
V2L
V3L
VAUXL
PWMSYNC (CONVST)
MODECTRL
REG <07>
CLK
MODECTRL REG
<09..10..11>
I
CONST
_TRIM
REG <2:0>
CAPACITOR RESET
Figure 11. ADC Overview
Single Slope ADC Operations
The ADC conversion process is done by comparing each ADC
input to a reference ramp voltage and timing the comparison of
the two signals. The actual conversion point is the time-point
intersection of the input voltage and the ramp voltage (VC), as
shown in Figure 12. This time is converted to counts by the 12-
bit ADC timer block and is stored in the ADC registers. The
ramp voltage used to perform the conversion is generated by
driving a fixed current into an off-chip capacitor, where the
capacitor voltage is:
V
I C
t
C
=
￥
(
)
Table V. Fundamental Characteristics of PWM Generation Unit of ADMCF341
Parameter
Min
Typ
Max
Unit
16-BIT PWM TIMER
Counter Resolution
Edge Resolution (Single Update Mode)
Edge Resolution (Double Update Mode)
Programmable Dead Time Range
Programmable Dead Time Increments
Programmable Pulse Deletion Range
Programmable Pulse Deletion Increments
PWM Frequency Range
PWMSYNC Pulsewidth (T
CRST
)
Gate Drive Chop Frequency Range
16
100
50
Bits
ns
ns
m
s
ns
m
s
ns
Hz
m
s
MHz
0
102
100
0
50
51
153
1
2.0
0.02
78,431
2
12.8
5
NOTES
1
153 Hz is calculated based on 16-bit resolution.
2
78,431 Hz is calculated based on 8-bit resolution.
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