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參數(shù)資料
| 型號： | ADMC401BST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Single-Chip, DSP-Based High Performance Motor Controller |
| 中文描述： | 24-BIT, 13 MHz, OTHER DSP, PQFP144 |
| 封裝： | PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 33/60頁 |
| 文件大小： | 417K |
| 代理商： | ADMC401BST |
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ADMC401
–33–
REV. B
PWMTM
PWMTM
[4
(GDCLK+1)]
2
PWMDT
2
PWMDT
PWMCHA
PWMCHA
AH
AL
Figure 26. Typical active LO PWM signals with high fre-
quency gate chopping enabled on both high side and low
side switches.
PWM Polarity Control, PWMPOL Pin
The polarity of the PWM signals produced at the output pins
AH to CL may be selected in hardware by the PWMPOL pin.
Connecting the PWMPOL pin to DGND selects active LO
PWM outputs, such that a LO level is interpreted as a com-
mand to turn on the associated power device. Conversely, con-
necting the PWMPOL pin to V
DD
selects active HI PWM and
the associated power devices are turned ON by a HI level at the
PWM outputs. There is an internal pull-up on the PWMPOL
pin, so that if this pin becomes disconnected (or is not connected),
active HI PWM will be produced. The level on the PWMPOL
pin may be read from Bit 2 of the SYSSTAT register, where a
zero indicates a measured LO level at the PWMPOL pin.
SWITCHED RELUCTANCE MODE
The PWM block of the ADMC401 contains a switched reluc-
tance (SR) mode that is controlled by the
PWMSR
pin. The
switched reluctance mode is enabled by connecting the
PWMSR
pin to DGND. In this SR mode, the low side PWM signals from
the three-phase timing unit assume permanently ON states,
independent of the value written to the duty-cycle registers. The
duty cycles of the high side PWM signals from the timing unit
are still determined by the three duty cycle registers. Using the
crossover feature of the output control unit, it is possible to
divert the permanently ON PWM signals to either the high-side
or low-side outputs. This mode is necessary because in the typi-
cal power converter configuration for switched or variable reluc-
tance motors, the motor winding is connected between the two
power switches of a given inverter leg. Therefore, in order to
build up current in the motor winding, it is necessary to turn on
both switches at the same time. Typical active LO PWM signals
during operation in SR mode are shown in Figure 27 for opera-
tion in double update mode. It is clear that the three low-side
signals (AL, BL and CL) are permanently ON and the three high
side signals are modulated in the usual manner so that the cor-
responding high side power switches are switched between the
ON and OFF states. The SR mode can
only
be enabled by con-
necting the
PWMSR
pin to GND. There is no software means
by which this mode can be enabled. There is an internal pull-up
resistor on the
PWMSR
pin so that if this pin is left unconnected
or becomes disconnected the SR mode is disabled. Of course,
the SR mode is disabled when the
PWMSR
pin is tied to V
DD
.
PWMCHA
1
PWMTM
AH
AL
BH
CH
BL
CL
PWMCHA
2
PWMCHB
2
PWMCHB
1
PWMCHC
2
PWMCHC
1
PWMTM
Figure 27. Active LO PWM signals in SR Mode
(PWMPOL
=
PWMSR
=
DGND) for ADMC401 in double update mode.
PWM SHUTDOWN
In the event of external fault conditions, it is essential that the
PWM system be instantaneously shutdown in a safe fashion. A
low level on the
PWMTRIP
pin provides an instantaneous,
asynchronous (independent of the DSP clock) shutdown of the
PWM controller. All six PWM outputs are placed in the OFF
state (as defined by the PWMPOL pin).
Note, however, when
the
PWMSR
pin is in the SR mode, the three low side PWM
signals from the three-phase timing unit will remain in the ON
state.
In addition, the PWMSYNC pulse is disabled and the
associated interrupt is stopped. The
PWMTRIP
pin has an
internal pull-down resistor so that if the pin becomes uncon-
nected the PWM will be disabled. The state of the
PWMTRIP
pin can be read from Bit 0 of the SYSSTAT register.
The 12 PIO lines of the ADMC401 can also be configured to
operate as PWM shutdown pins using the PIOPWM register.
The 12-bit PIOPWM has a control bit for each PIO line (Bit 0
controls PIO0, etc.). Setting the control bit enables the corre-
sponding PIO line as a PWM shutdown pin. A falling edge on
the PIO line will then generate an instantaneous, asynchronous
shutdown of the PWM system, in a manner identical to the
PWMTRIP
pin. Also like
PWMTRIP
, all of the PIO lines have
internal pull-down resistors, so that if a PIO pin becomes uncon-
nected and is configured as a PWM shutdown pin, the PWM will
be disabled. Following a reset, all PIO lines are configured as
inputs, have pull-downs and are programmed as PWM shut
down pins (PIOPWM = 0x0FFF) so that the PWM is shut-
down. Correct operation of the PWM is not possible without
first correctly configuring the PIO system.
In addition, it is possible to initiate a PWM shutdown in soft-
ware by writing to the 1-bit PWMSWT register. The act of
writing to this register generates a PWM shutdown command in
a manner identical to the
PWMTRIP
or PIO pins. A hardware
trip has no effect on the PWMSWT register. It does not matter
which value is written to the PWMSWT register. However,
following a PWM shutdown, it is possible to read the PWMSWT
register to determine if the shutdown was generated by hard-
ware or software. If the PWM shutdown was caused by the
PWMSWT register, a 1 will be read back from the PWMSWT
register. Reading the PWMSWT register automatically clears
its contents.
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