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參數(shù)資料
| 型號： | ADM1069AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP32 |
| 封裝： | MS-026-BBA, LQFP-32 |
| 文件頁數(shù)： | 13/36頁 |
| 文件大小： | 763K |
| 代理商： | ADM1069AST |
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ADM1069
Rev. A | Page 20 of 36
Sequence Detector
The sequence detector block is used to detect when a step in a
sequence has been completed. It looks for one of the SE inputs
to change state, and is most often used as the gate on successful
progress through a power-up or power-down sequence. A timer
block is included in this detector, which can insert delays into a
power-up or power-down sequence, if required. Timer delays
can be set from 10 μs to 400 ms. Figure 27 is a block diagram of
the sequence detector.
04735-032
SUPPLY FAULT
DETECTION
LOGIC INPUT CHANGE
OR FAULT DETECTION
WARNINGS
FORCE FLOW
(UNCONDITIONAL JUMP)
VP1
VX4
INVERT
SEQUENCE
DETECTOR
SELECT
TIMER
Figure 27. Sequence Detector Block Diagram
The sequence detector can also help to identify monitoring
faults. In the sample application shown in Figure 26, the FSEL1
and FSEL2 states first identify which of the VP1,VP2, or VP3
pins has faulted, and then they take the appropriate action.
Monitoring Fault Detector
The monitoring fault detector block is used to detect a failure
on an input. The logical function implementing this is a wide
OR gate, which can detect when an input deviates from its
expected condition. The clearest demonstration of the use of
this block is in the PWRGD state, where the monitor block
indicates that a failure on one or more of the VP1,VP2, or VP3
inputs has occurred.
No programmable delay is available in this block because the
triggering of a fault condition is likely to be caused by a supply
falling out of tolerance. In this situation, the user needs to react as
quickly as possible. Some latency occurs when moving out of this
state, however, because it takes a finite amount of time (~20 μs) for
the state configuration to download from EEPROM into the SE.
Figure 28 is a block diagram of the monitoring fault detector.
04735-033
SUPPLY FAULT
DETECTION
LOGIC INPUT CHANGE
OR FAULT DETECTION
VP1
VX4
MONITORING FAULT
DETECTOR
MASK
SENSE
1-BIT FAULT
DETECTOR
FAULT
WARNINGS
MASK
1-BIT FAULT
DETECTOR
FAULT
MASK
SENSE
1-BIT FAULT
DETECTOR
FAULT
Figure 28. Monitoring Fault Detector Block Diagram
Timeout Detector
The timeout detector allows the user to trap a failure to make
proper progress through a power-up or power-down sequence.
In the sample application shown in Figure 26, the timeout next-
state transition is from the EN3V3 and EN2V5 states. For the
EN3V3 state, the signal 3V3ON is asserted upon entry to this
state (on the PDO1 output pin) to turn on a 3.3 V supply. This
supply rail is connected to the VP2 pin, and the sequence detec-
tor looks for the VP2 pin to go above its UV threshold, which is
set in the supply fault detector (SFD) attached to that pin.
The power-up sequence progresses when this change is
detected. If, however, the supply fails (perhaps due to a short
circuit overloading this supply), the timeout block traps the
problem. In this example, if the 3.3 V supply fails within 10 ms,
the SE moves to the DIS3V3 state and turns off this supply by
bringing PDO1 low. It also indicates that a fault has occurred by
taking PDO3 high. Timeout delays from 100 μs to 400 ms can
be programmed.
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