參數(shù)資料
型號(hào)： ADM1060
廠商： Analog Devices, Inc.
英文描述： DIP Socket; No. of Contacts:56; Pitch Spacing:0.07"; Row Spacing:0.6"; Terminal Type:PC Board; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes
中文描述： 通信系統(tǒng)監(jiān)控/排序電路
文件頁數(shù)： 7/45頁
文件大?。?/td> 303K
代理商： ADM1060
ADM1060 INPUTS
ADM1060
–7–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
ADM1060 INPUTS
POWE RING T HE ADM1060
T he ADM1060 is powered from the highest voltage input
on either the Positive Only supply inputs (VPn) or the
High Voltage supply input (VH). T he same pins are used
for supply fault detection (discussed below) . A V
DD
Arbi-
trator on the device chooses which supply to use. T he
arbitrator can be considered to be diode OR
’
ing the posi-
tive supplies together (as shown in figure 1). In addition
to this, the diodes are supplemented with switches in a
synchronous rectifier manner, to minimise voltage loss.
T his loss can be reduced to ~0.2V, resulting in the ability
to power the ADM1060 from a supply as low as 3.0V.
Note that the supply on the VBn pins cannot be used to
power the device, even if the input on these pins is posi-
tive. Also, the minimum supply of 3.0V must appear on
one of the VPn pins in order to power up the ADM1060
correctly. A supply of no less than 4.5V can be used on
VH. T his is because there is no synchronous rectifier
circuit on the VH pin, resulting in a voltage drop of ~1.5V
across the diode of the V
DD
Arbitrator.
An external cap to GND is required to decouple the on-
chip supply from noise. T his cap should be connected to
the VDDCAP pin, as shown in figure 1. T he cap has
another use during
“
brown outs
”
(momentary loss of
power). Under these conditions, where the input supply,
VPn, dips transiently below V
DD
, the synchronous rectifier
switch immediately turns off so that it doesn
’
t pull V
DD
down. T he V
DD
cap can then act like a reservoir and keep
the chip active until the next highest supply takes over the
powering of the device. 0.1 F is recommended for this
function.
Note that in the case where there are 2 or more supplies
within 100mV of each other, the supply which takes con-
trol of V
DD
first will keep control (e.g) if VP1 is con-
nected to a 3.3V supply, then V
DD
will power up to
approximately 3.1V through VP1. If VP2 is then con-
nected to another 3.3V supply, VP1 will still power the
device, unless VP2 goes 100mV higher than VP1.
!"
Figure 1. VDD Arbitrator Operation
PROGRAMMABLE SUPPLY FAULT DE T E CT ORS
(SF D
’
S)
T he ADM1060 has seven programmable Supply Fault
Detectors, 1 high voltage detector (2V to 14.4V), 2 bipo-
lar detectors (2V to 6V, -2V to -6V) and 4 Positive only
voltage detectors (0.6V to 6V). Inputs are applied to these
detectors via the VH (High Voltage Supply input) pin,
VBn (Bipolar Supply input) pins and VPn (Positive Only
input) pins respectively. T he SFD
’
s detect a fault condi-
tion on any of these input supplies. A fault is defined as
Undervoltage (where the supply drops below a
preprogrammed level), Overvoltage (where the supply
rises above a preprogrammed level) or Out-of-Window
(where the supply deviates outside either the programmed
overvoltage OR undervoltage threshold). Only one fault
type can be selected at a time.
An Undervoltage fault is detected by comparing the input
supply to a programmed reference (the undervoltage
threshold). If the input voltage drops below the
undervoltage threshold the output of the comparator goes
high, asserting a fault. T he undervoltage threshold is
programmed using an 8 bit DAC. On a given range, the
UV threshold can be set with a resolution of:-
Step Size = Threshold Range/255
An Overvoltage (OV) fault is detected in exactly the same
way, using a second comparator and DAC to program the
reference.
All thresholds are programmed using 8 bit registers, one
register each for the 7 UV thresholds and 1 each for the 7
OV thresholds. T he UV or OV threshold programmed by
the user is given by:-
V
T
= V
R
x N + V
B
255
where:-
V
T
= Desired T hreshold Voltage (UV or OV)
V
R
= T hreshold Voltage Range
N = Decimalized version of 8 bit code
V
B
= Bottom of T hreshold Range
T his results in the code for a given threshold being given
by:-
N=255 x (V
T
- V
B
)/V
R
T hus, for example, if the user wishes to set a 5V OV
threshold on VP1, the code to be programmed in the
PS1OVT H register (discussed later) would be given by:-
N=255 x (5-2)/4
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