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| 型號： | ADM1060 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DIP Socket; No. of Contacts:56; Pitch Spacing:0.07"; Row Spacing:0.6"; Terminal Type:PC Board; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes |
| 中文描述： | 通信系統(tǒng)監(jiān)控/排序電路 |
| 文件頁數(shù)： | 15/45頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ADM1060 |
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ADM1060 INPUTS
ADM1060
–
15
–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
GE NE R A L PUR POSE INPUT S (GPI
’
S)
T he ADM1060 has 4 General Purpose Logic Inputs
(GPI
’
s). T hese are T T L /CMOS logic level compatible.
Standard logic signals can be applied to the pins (eg)
RESET from reset generators, PWRGOOD signals, Fault
flags, Manual Resets etc. T hese signals can be gated with
the other inputs supervised by the ADM1060, and used to
control the status of the PDO
’
s. T he inputs can be simply
buffered, or a logic transition can be detected and a pulse
output generated. T he width of this pulse is
programmable from 10 s to a maximum of 10ms. T he
configuration of the GPI
’
s is shown in the register and
bitmaps below.
T he GPI
’
s also feature a glitch filter, similar to that
provided on the SFD
’
s. T his enables the user to ignore
spurious transitions on the GPI
’
s. For example, the glitch
T ABLE 20. LIST OF RE GIST E RS FOR T HE GE NE RAL PURPOSE INPUT S (GPIN)
Hex
T able
Name
D efault
Description
Address
Power On Value
98
G PI4C F G
00h
Setup of the glitch filter delay, pulse width, level/edge
detection etc. configuration of GPI4
99
G PI3C F G
00h
Setup of the glitch filter delay, pulse width, level/edge
detection etc. configuration of GPI3
9A
G PI2C F G
00h
Setup of the glitch filter delay, pulse width, level/edge
detection etc. configuration of GPI2
9B
G PI1C F G
00h
Setup of the glitch filter delay, pulse width, level/edge
detection etc. configuration of GPI1
T ABL E 21. BIT MAP F OR GPInC F G RE GIST E RS (POWE R- ON D E F AUL T 00H)
Bit
Name
R/W
Description
7
Reserved
N/A
Cannot be used
6
INV IN
R /W
If high, invert Input
5
IN T Y P
R /W
Determines whether a level or an edge is detected on the pin. If an edge
is detected then positive pulse of programmable length is outputted
INT Y P
D etect
0
Detect level
1
Detect edge
4-3
PU L S1-0
R /W
Length of pulse outputted once an edge has been detected on input
P U L S 1
P U L S 0
Pulse L ength Selected (
0
0
10
0
1
100
1
0
1000
1
1
10000
s)
2-0
G F 2-G F 0
R /W
Length of time for which the input is ignored
GF2
GF1
GF0
Glitch Filter Delay ( s)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
5
10
20
30
50
75
100
filter can be used to debounce a Manual Reset switch.
T he length of the glitch filter can also be programmed.
L OGIC ST AT E OF T HE GPI
’
S (AND OT HE R L OGIC
INP U T S )
Each of the GPI
’
s has a weak (10 A) pull-down current
source. T he current sources can be connected to the
inputs by progamming the relevant bit in a register
(PDEN). T his enables the user to control the condition
of these inputs, pulling them to GND, even when they are
unused or left floating.
Note that the same pull- down function is provided for the
SMBus address pins, A0 and A1 and for the WDI pin. A
register is used to program which of the inputs is
connected to the current sources.
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