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參數(shù)資料
| 型號： | ADM1033ARQ-REEL |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 2Cel, RECTANGULAR, SURFACE MOUNT |
| 封裝： | MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 4/39頁 |
| 文件大?。?/td> | 819K |
| 代理商： | ADM1033ARQ-REEL |
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ADM1033
Rev. 0 | Page 12 of 40
SMBus 2.0 FIXED-AND-DISCOVERABLE MODE
The ADM1033 supports fixed-and-discoverable mode, which is
backward-compatible with SMBus 1.0 and 1.1. Fixed-and-
discoverable mode supports all the same functionality as ARP-
capable mode, except for assign address—in which case it
powers up with a fixed address and is not changed by the assign
address call. The fixed address is determined by the state of the
LOCATION pin on power-up.
SMBus 2.0 READ AND WRITE OPERATIONS
The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial data
line (SDA) while the serial clock line (SCL) remains high. This
indicates that an address/data stream is to follow. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, which consist of a 7-
bit address (MSB first) plus an R/W bit. The last bit determines
the direction of the data transfer (whether data is written to or
read from the slave device).
1. The peripheral that corresponds to the transmitted address
responds by pulling the data line low during the low period
before the 9th clock pulse. This pulse is known as the
acknowledge bit. All other devices on the bus remain idle
while the selected device waits for data to be read from or
written to it. If the R/W bit is a 0, the master writes to the
slave device. If the R/W bit is a 1, the master reads from it.
2. Data is sent over the serial bus in sequences of nine clock
pulses—eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, as a low-to-high transition
when the clock is high might be interpreted as a stop
signal. The number of data bytes that can be transmitted
over the serial bus in a single read or write operation is
limited only by what the master and slave devices can
handle.
3. When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the tenth clock pulse to assert a
stop condition. In read mode, the master device overrides
the acknowledge bit by pulling the data line high during
the low period before the ninth clock pulse. This is known
as no acknowledge. The master takes the data line low
during the low period before the tenth clock pulse, then
high during the tenth clock pulse to assert a stop condition.
It is not possible to mix read and write in one operation,
because the type of operation is determined at the beginning
and cannot be changed without starting a new operation.
To write data to one of the device data registers or read data
from it, the address pointer register (APR) must be set so that
the correct data register is addressed. The first byte of a write
operation always contains an address that is stored in the APR.
If data is to be written to the device, the write operation
contains a second data byte. The second data byte is written to
the register selected by the APR.
As shown in Figure 18, the device address is sent over the bus,
followed by R/W set to 0. This is followed by two data bytes.
The first data byte is the address of the designated internal data
register, which is stored in the APR. The second data byte is the
data to be written to the internal data register.
When reading data from a register there are two possibilities:
If the ADM1033’s APR value is unknown or incorrect, it
must be set to the correct value before data can be read
from the desired data register. To do this, perform a write
to the ADM1033 as before; but this time send only the data
byte containing the register. (See Figure 19.) A read
operation is then performed. With the serial bus address
and the R/W bit set to 1, the data byte is read from the data
register. (See Figure 20.)
If the APR is known to be already at the desired address,
data can be read from the corresponding data register
without first writing to the APR. In this case, Figure 19 can
be omitted.
In Figure 18 to Figure 20, the serial bus address is determined
by the state of the LOCATION pin on power-up.
Rev. 1 | Page 12 of 39 | www.onsemi.com
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| ADM1033ARQ-REEL7 | 功能描述:IC THERM/FAN SPEED CTRLR 16-QSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 熱管理 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 功能:溫度監(jiān)控系統(tǒng)（傳感器） 傳感器類型:內(nèi)部和外部 感應(yīng)溫度:-40°C ~ 125°C，外部傳感器 精確度:±2.5°C 本地（最大值），±5°C 遠(yuǎn)程（最大值） 拓?fù)?ADC，比較器，寄存器庫 輸出類型:2 線 SMBus? 輸出警報(bào):無 輸出風(fēng)扇:無 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-8 供應(yīng)商設(shè)備封裝:SOT-23-8 包裝:Digi-Reel® 其它名稱:296-22675-6 |
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