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參數(shù)資料
| 型號： | ADG796ABCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX/DEMUX HEX 2X1 24LFCSP |
| 產(chǎn)品變化通告： | ADG79xx Discontinuance Notice 17/Aug/2010 |
| 標準包裝： | 1 |
| 功能： | 多路復用器/多路分解器 |
| 電路： | 6 x 2:1 |
| 導通狀態(tài)電阻： | 4 歐姆 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3V，5V |
| 電流 - 電源： | 1nA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 801 (CN2011-ZH PDF) |
| 其它名稱： | ADG796ABCPZ-REELDKR |
ADG796A
Rev. 0 | Page 19 of 24
LDSW BIT
The LDSW bit allows the user to control the way the device
executes the commands loaded during write operations. The
ADG796A executes all commands loaded between two
successive write operations that have set the LDSW bit high.
Setting the LDSW high for every write cycle ensures that the
device executes the command immediately after the LDSW bit
is loaded into the device. This setting can be used when the
desired configuration is achieved by sending a single command
or when the switches are not required to be updated at the same
time. When the desired configuration requires multiple
commands with simultaneous updates, the LDSW bit should be
set low while loading the commands, except for the last one
when the LDSW bit should be set high. Once the last command
with LDSW = high is loaded, the device simultaneously
executes all commands received since the last update.
POWER ON/SOFTWARE RESET
The ADG796A has a software reset function implemented by
the RESETB bit from the second data byte loaded into the device
during a write operation. For normal operation of the multi-
plexers, this bit should be set high. When RESETB = low or after
power-up, the switches from all multiplexers are turned off (open).
READ OPERATION
When reading data back from the ADG796A, the user must
begin with an address byte and R/W bit. Then, the switch
acknowledges that it is prepared to transmit data by pulling
SDA low. Following this acknowledgement, the ADG796A
transmits two bytes on the next clock edges. These bytes contain
the status of the switches, and each byte is followed by an
acknowledge bit. A logic high bit represents a switch in the on
(close) state while a low represents a switch in the off (open)
state. Figure 28 illustrates the entire read sequence.
The bit map accompanying Figure 28 shows the relationship
between the elements of the ADG796A and the bits that
represent their status after a completed read operation.
ADG796 Bit Map
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
S1A/D1
S1B/D1
S2A/D2
S2B/D2
S3A/D3
S3B/D3
S4A/D4
S4B/D4
S5A/D5
S5B/D5
S6A/D6
S6B/D6
-
SCL
SDA
A1
A0
RB14
RB15
R/W
RB13 RB12 RB11 RB10 RB9 RB8
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
START
CONDITION
BY MASTER
STOP
CONDITION
BY MASTER
ADDRESS BYTE
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH
06
03
6-
01
5
Figure 28. Read Operation
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