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參數(shù)資料
| 型號(hào)： | ADF4001BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | 200 MHz Clock Generator PLL |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 190K |
| 代理商： | ADF4001BRU |
REV. 0
ADF4001
–
6
–
CIRCUIT DESCRIPTION
Reference Input Section
The reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
POWER-DOWN
CONTROL
TO
R COUNTER
NC
NO
SW1
SW3
SW2
NC
100k
REF
IN
BUFFER
Figure 2. Reference Input Stage
RF Input Stage
The RF input stage is shown in Figure 3. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the N Counter buffer.
RF
IN
B
RF
IN
A
2k
AGND
AV
DD
BIAS
GENERATOR
2k
1.6V
Figure 3. RF Input Stage
N Counter
The N CMOS counter allows a wide ranging division ratio
in the PLL feedback counter. Division ratios of 1 to 8191
are allowed.
N and R Relationship
The N counter, in conjunction with the R Counter make it
possible to generate output frequencies that are spaced only by
the Reference Frequency divided by R. The equation for the
VCO frequency is as follows:
f
VCO
=
N
/
R
×
f
REFIN
f
VCO
Output Frequency of external voltage-controlled oscil-
lator (VCO).
N
Preset Divide Ratio of binary 13-bit counter (1 to 8,191).
f
REFIN
External reference frequency oscillator.
R
Preset divide ratio of binary 14-bit programmable refer-
ence counter (1 to 16,383).
TO PFD
13-BIT N
COUNTER
FROM
N COUNTER LATCH
FROM RF
INPUT STAGE
Figure 4. N Counter
R Counter
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic. The
PFD includes a programmable delay element which controls the
width of the antibacklash pulse. This pulse ensures that there is
no deadzone in the PFD transfer function and minimizes phase
noise and reference spurs. Two bits in the Reference Counter
Latch, ABP2 and ABP1 control the width of the pulse. See
Table III.
DELAY
R DIVIDER
N DIVIDER
CP OUTPUT
HI
HI
CPGND
V
P
CHARGE
PUMP
UP
CP
DOWN
N DIVIDER
R DIVIDER
D1
Q1
U1
CLR1
D2
CLR2
Q2
U2
U3
Figure 5. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4110 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the Function
Latch. Table V shows the full truth table. Figure 6 shows the
MUXOUT section in block diagram form.
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