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參數(shù)資料
| 型號(hào)： | ADF4001BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | 200 MHz Clock Generator PLL |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 190K |
| 代理商： | ADF4001BRU |
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REV. 0
ADF4001
–
4
–
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
1
R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is
I
R
CP
AX
SET
M
=
23 5
So, with
R
SET
= 4.7 k
,
I
CP MAX
= 5 mA.
Charge Pump Output. When enabled, this provides
±
I
CP
to the external loop filter which, in turn, drives the
external VCO or VCXO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the N Counter. This point must be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF. See Figure 3.
Input to the N Counter. This small signal input is ac-coupled to the external VCO or VCXO.
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AV
DD
must be the same value as DV
DD.
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input resis-
tance of 100 k
.
See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator or can be
ac-coupled.
Digital Ground
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking the pin high will power up the device, depending on the status of the power-down bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high-impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is
a high-impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches, the latch being selected using the control bits.
This multiplexer output allows either the Lock Detect, the scaled RF, or the scaled Reference Frequency to
be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV
DD
must be the same value as AV
DD
.
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it
can be set to 5 V and used to drive a VCO or VCXO with a tuning range of up to 5 V.
2
CP
3
4
5
CPGND
AGND
RF
IN
B
6
7
RF
IN
A
AV
DD
8
REF
IN
9
10
DGND
CE
11
CLK
12
DATA
13
LE
14
MUXOUT
15
DV
DD
16
V
P
PIN CONFIGURATIONS
TRANSISTOR COUNT
6425 (CMOS) and 50 (Bipolar).
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
ADF4001
R
SET
LE
MUXOUT
DV
DD
V
P
CP
CPGND
AGND
CE
CLK
DATA
RF
IN
B
RF
IN
A
AV
DD
REF
IN
DGND
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
CPGND 1
AGND 2
AGND 3
RF
IN
B 4
RF
IN
A 5
2
A
D
A
D
R
I
D
D
1
S
1
P
1
D
1
D
PIN 1
ADF4001
TOP VIEW
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