參數(shù)資料
型號： ADE7754
廠商： Analog Devices, Inc.
英文描述： ADE7754
中文描述： ADE7754
文件頁數(shù)： 42/44頁
文件大小： 630K
代理商： ADE7754
REV. PrG 01/03
PRELIMINARY TECHNICAL DATA
ADE7754
–
42
–
Interrupt Mask Register (0Fh)
When an interrupt event occurs in the ADE7754, the
IRQ
logic output goes active low if the mask bit for this event is logic
one in this register. The IRQ logic output is reset to its default collector open state when the RSTATUS register is read. The
following describes the function of each bit in the Interrupt Mask Register.
Table XVI MASK Register
Bit
Location
Interrupt
Flag
Default
Value
Description
0
AEHF
0
Enables an interrupt when there is a 0 to 1 transition of the MSB of the AENERGY register
(i.e. the AENERGY register is half-full)
Enables an interrupt when there is a SAG on the line voltage of the Phase A
Enables an interrupt when there is a SAG on the line voltage of the Phase B
Enables an interrupt when there is a SAG on the line voltage of the Phase C
Enables an interrupt when there is a zero crossing time out detection on Phase A
Enables an interrupt when there is a zero crossing time out detection on Phase B
Enables an interrupt when there is a zero crossing time out detection on Phase C
Enables an interrupt when there is a rising zero crossing in voltage channel of the phase
A
—
Zero Crossing Detection
Enables an interrupt when there is a rising zero crossing in voltage channel of the phase
B
—
Zero Crossing Detection
Enables an interrupt when there is a rising zero crossing in voltage channel of the phase
C
—
Zero Crossing Detection
Enables an interrupt when the LAENERGY and LVAENERGY accumulations over
LINCYC are finished
Reserved
Enables an interrupt when the voltage input selected in the MMODE register is above the
value in the PKVLVL register
Enables an interrupt when the current input selected in the MMODE register is above the
value in the PKILVL register.
Enables an interrupt when a data is present in the Waveform Register.
Enables an interrupt when there is a 0 to 1 transition of the MSB of the VAENERGY
register (i.e. the VAENERGY register is half-full)
1
2
3
4
5
6
7
SAGA
SAGB
SAGC
ZXTOA
ZXTOB
ZXTOC
ZXA
0
0
0
0
0
0
0
8
ZXB
0
9
ZXC
0
Ah
LENERGY
0
Bh
Ch
PKV
0
Dh
PKI
0
Eh
Fh
WFSM
VAEHF
0
0
INTERRUPT MASK REGISTER*
ADDR: 0Fh
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
8
9
A
B
C
D
E
F
0
0
0
0
0
0
0
0
(Apparent Energy Register HVAEHF
AEHF
(Active Energy Register Half Full)
SAG
(SAG Event Detect)
ZX
(Zero Crossing Time out Detection)
WFMP
(New Waveform Sample Ready)
*Register contents show power on defaults
PKV
LENERGY
(End of the LAENERGY and LVAENERGY accumulation)
ZX
(Zero Crossing Detection)
PKI
(Current channel Peak detection)
(Voltage channel Peak Reserved
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ADE7754ARZ 功能描述:IC ENERGY METERING 3PHASE 24SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 能量測量 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:*
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