參數(shù)資料
型號： ADE7169ASTZF16
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver
中文描述： SPECIALTY ANALOG CIRCUIT, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-22-VMMD-4, LFCSP-64
文件頁數(shù)： 71/140頁
文件大小： 1359K
代理商： ADE7169ASTZF16
Preliminary Technical Data
ADE7169F16
8052 MCU CORE ARCHITECTURE
The ADE7169F16 has an 8052 MCU core and uses the 8051
instruction set. Some of the standard 8052 peripherals, such as
the UART, have been enhanced. This section describes the
standard 8052 core and enhancements that have been made to it
in the ADE7169F16.
Rev. PrD | Page 71 of 140
The special function register (SFR) space is mapped into the
upper 128 bytes of internal data memory space and is accessed
by direct addressing only. It provides an interface between the
CPU and all on-chip peripherals. A block diagram showing the
programming model of the ADE7169F16 via the SFR area is
shown in Figure 54.
All registers except the program counter (PC), instruction
register (IR) and the four general-purpose register banks reside
MCU REGISTERS
The registers used by the MCU are summarized hereafter.
Table 52. 8051 SFRs
SFR
Address
Bit Addressable
in the SFR area. The SFR registers include control,
configuration, and data registers that provide an interface
between the CPU and all on-chip peripherals.
OTHER ON-CHIP
PERIPHERALS:
SERIAL I/O
WDT
TIMERS
BATTERY ADC
TEMPERATURE ADC
LCD DRIVER
RTC
POWER MANAGEMENT
ENERGY MEASUREMENT
16-kBYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE PROGRAM/DATA
MEMORY
256 BYTES XRAM
IR
PC
8051
COMPATIBLE
CORE
STACK
REGISTER
BANKS
256 BYTES
GENERAL
PURPOSE
RAM
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
Figure 54: ADE7169F16 Block Diagram
Description
A
0xE0
Yes
Accumulator
B
0xF0
Yes
Auxiliary Math register
PSW
0xD0
Yes
Program status word - see Table 53
PCON
0x87
No
Power Control register – see Table 54
DPL
0x82
No
Data pointer LSByte – see Table 55
DPH
0x83
No
Data pointer MSbyte – see Table 56
SP
0x81
No
Stack pointer LSB byte – see Table 57
CFG
0xAF
No
Configuration register – see Table 58
Table 53. Program Status Word SFR (PSW, 0xD0)
Bit Location
Bit Addr.
7
0xD7
6
0xD6
5
0xD5
4-3
0xD4,
0xD3
Bit Name
CY
AC
F0
RS1, RS0
Description
Carry Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
Auxiliary Carry Flag. Modified by ADD, and ADDC instructions.
General-Purpose Flag availble to the user
Register Bank Select Bits.
RS1
RS0
Selected Bank
0
0
0
0
1
1
1
0
2
1
1
3
Overflow Flag. Modified by ADD, ADDC, SUBB, MUL and DIV instructions.
General-Purpose Flag availble to the user.
Parity Bit. The number of bits set in the Accumulator added to the value of the parity bit
will always be an even number.
2
1
0
0xD2
0xD1
0xD0
OV
F1
P
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