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參數(shù)資料
| 型號(hào)： | ADE7169ASTZF16 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-22-VMMD-4, LFCSP-64 |
| 文件頁(yè)數(shù)： | 103/140頁(yè) |
| 文件大?。?/td> | 1359K |
| 代理商： | ADE7169ASTZF16 |
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Preliminary Technical Data
ADE7169F16
TIMERS
The ADE7169F16 has three 16-bit timer/ counters: Timer 0,
Timer 1, and Timer 2. The timer/counter hardware is included
on-chip to relieve the processor core of the overhead inherent in
implementing timer/counter functionality in software. Each
timer/counter consists of two 8-bit registers: THx and TLx (x =
0, 1, or 2). All three can be configured to operate either as
timers or as event counters.
Rev. PrD | Page 103 of 140
When functioning as a timer, the TLx register is incremented
every machine cycle. Thus, one can think of it as counting
machine cycles. Because a machine cycle on a single-cycle core
consists of one core clock period, the maximum count rate is
the core clock frequency.
Table 93. Timer SFRs
SFR
Address
Bit Addressable
When functioning as a counter, the TLx register is incremented
by a 1-to-0 transition at its corresponding external input pin:
T0, T1, or T2. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. Because it takes
two machine cycles (two core clock periods) to recognize a
1-to-0 transition, the maximum count rate is half the core clock
frequency.
There are no restrictions on the duty cycle of the external input
signal, but, to ensure that a given level is sampled at least once
before it changes, it must be held for a minimum of one full
machine cycle. User configuration and control of all timer
operating modes is achieved via the SFRs in Table 93.
Description
TCON
0x88
Yes
Timer0 and Timer1 Control Register – see Table 95
TMOD
0x89
No
Timer Mode register– see Table 94
TL0
0x8A
No
Timer0 LSB– see Table 98
TL1
0x8B
No
Timer1 LSB– see Table 100
TH0
0x8C
No
Timer0 MSB– see Table 97
TH1
0x8D
No
Timer1 MSB– see Table 99
T2CON
0xC8
Yes
Timer2 Control Register – see Table 96
RCAP2L
0xCA
No
Timer2 Reload/Capture LSB – see Table 104
RCAP2H
0xCB
No
Timer2 Reload/Capture MSB – see Table 103
TL2
0xCC
No
Timer2 LSB – see Table 102
TH2
TIMER SFR REGISTER LIST
Table 94. Timer/Counter 0 and 1 Mode SFR (TMOD, 0x89)
Bit
Location
Mnemonic
Value
7
Gate1
0
0xCD
No
Timer2 MSB – see Table 101
Bit
Default
Description
Timer 1 Gating Control.
Set by software to enable Timer/Counter 1 only while the INT1 pin is high and the TR1 control is
set.
Cleared by software to enable Timer 1 whenever the TR1control bit is set.
Timer 1 Timer or Counter Select Bit.
Set by software to select counter operation (input from T1 pin).
Cleared by software to select the timer operation (input from internal system clock).
Timer 1 Mode Select bits
M1
M0
Description
6
C_T1
0
0
0
0
1
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
5-4
T1_M1,
T1_M0
00
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