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參數(shù)資料
| 型號： | ADDI7100BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD SIGNAL7 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | CCD 信號處理器，12 位 |
| 應(yīng)用： | 數(shù)碼相機(jī) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
ADDI7100
Rev. C | Page 13 of 20
ANALOG-TO-DIGITAL CONVERTER (ADC)
The ADDI7100 uses a high performance ADC architecture
optimized for high speed and low power. Differential non-
linearity (DNL) performance is typically better than 0.5 LSB.
The ADC uses a 2 V full-scale input range.
VARIABLE GAIN AMPLIFIER (VGA)
The VGA stage provides a gain range of 6 dB to 42 dB, pro-
grammable with 10-bit resolution through the serial digital
interface. The minimum gain of 6 dB is needed to match a 1 V
input signal with the ADC full-scale range of 2 V. A plot of the
VGA gain curve is shown in Figure 13.
VGA Gain (dB) = (VGA Code × 0.0358 dB) + 5.4 dB
where Code is in the range of 0 to 1023.
VGA GAIN REGISTER MODE
42
12
383
127
V
G
A
GA
IN
(
d
B
)
0
30
255
36
24
18
6
511
639
767
895
1023
0
76
08
-01
1
Figure 13. VGA Gain Curve
DIGITAL DATA OUTPUTS
By default, the digital output data is latched by the rising edge of
the DATACLK input. Output data timing is shown in Figure 3.
It is also possible to make the output data latch transparent,
immediately validating the data outputs from the ADC. Setting
the DOUTLATCH register (Address 0x01[5]) to 1 configures
the latch as transparent. The data outputs can also be disabled
by setting the DOUT_OFF register (Address 0x01[4]) to 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADDI9000BBCZRL | 制造商:Analog Devices 功能描述: |
| ADDI9000BCBZRL | 制造商:Analog Devices 功能描述:DRIVER |
| ADDI9000XCBZ | |
| ADDI9001BBCZ | 制造商:Analog Devices 功能描述: |
| ADDI9001BBCZRL | 制造商:Analog Devices 功能描述: |
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