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參數(shù)資料
| 型號： | ADDI7100BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD SIGNAL7 32LFCSP |
| 標準包裝： | 1 |
| 類型： | CCD 信號處理器，12 位 |
| 應用： | 數(shù)碼相機 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
ADDI7100
Rev. C | Page 17 of 20
COMPLETE REGISTER LISTING
Note that when an address contains fewer than 16 data bits, all remaining bits must be written as zeros.
Table 8. AFE
Address
Data
Bits
Default
Value
Type1
Name
Description
0x00
[1:0]
0
SCK
STANDBY
00: normal operation
01: reference standby
10: full standby
11: full standby
[2]
0x1
CLAMP_EN
1: enable black clamp
0: disable black clamp
[3]
0
FASTCLAMP
0: normal CLPOB settling
1: faster CLPOB settling
[4]
0
FASTUPDATE
1: enable very fast clamping when CDS gain is changed
0: ignore CDS gain updates
[5]
0
PBLK_LVL
0: blank to 0
1: blank to clamp level
[6]
0
DCBYP
0: normal dc restore operation
1: dc restore disabled during PBLK active
[8:7]
0x2
Test
Test use only; must be set to 2
[10:9]
0x2
Test
Test use only; must be set to 2
0x01
[0]
0
SCK
SHPD_POL
0: rising edge sample
1: falling edge sample
[1]
0
DATACLK_POL
0: rising edge triggered
1: falling edge triggered
[2]
0
CLP_POL
0: active low
1: active high
[3]
0
PBLK_POL
0: active low
1: active high
[4]
0
DOUT_OFF
0: data outputs are driven
1: data outputs are disabled (high-Z)
[5]
0
DOUTLATCH
0: retime data outputs with output latch (using DATACLK)
1: do not retime data outputs; output latch is transparent
[6]
0
GRAY_EN
1: gray encode ADC outputs
0x02
[2:0]
0x1
SCK/VD
CDSGAIN
CDS gain setting:
0x0: 3 dB
0x1: 0 dB
0x2: +3 dB
0x3: +6 dB
0x03
[9:0]
0x0F
SCK/VD
VGAGAIN
VGA gain, 6 dB to 42 dB (0.0358 dB per step)
0x04
[10:0]
0x1EC
SCK/VD
CLAMPLEVEL
Optical black clamp level, 0 LSB to 511 LSB (0.25 LSB per step)
0x05
[1:0]
0
SCK
STARTUP
Must be set to 0x3 after power-up
[3:2]
0
Test
Test use only; must be set to 0
0x06
[2:0]
0x6
SCK
Test
Test use only; must be set to 6
[3]
0
Test
Test use only; must be set to 0
[5:4]
0
Test
Test use only; must be set to 0
0x07
[0]
0
SCK
Test
Test use only; must be set to 0
0x08
[11:0]
0xFFF
SCK
Test
Test use only; must be set to 0xFFF
0x09
[11:0]
0xFFF
SCK
Test
Test use only; must be set to 0xFFF
0x0A
[0]
0
SCK
Test
Test use only; must be set to 0
0x0B
[0]
0
SCK
SW_RST
1: software reset; automatically resets to 0 after software reset
0x0C
[0]
0x1
SCK
OUTCONTROL
Data output control:
0: make all outputs dc inactive
1: enable data outputs
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| ADDI7100BCPZRL | 功能描述:IC PROCESSOR CCD SIGNAL7 32LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| ADDI9000BBCZRL | 制造商:Analog Devices 功能描述: |
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