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參數(shù)資料
| 型號： | ADDI7100BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD SIGNAL7 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號處理器，12 位 |
| 應(yīng)用： | 數(shù)碼相機(jī) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
ADDI7100
Rev. C | Page 16 of 20
SERIAL INTERFACE TIMING
All ADDI7100 internal registers are accessed through a 3-wire
serial interface. Each register consists of an 8-bit address and
a 16-bit data-word. Both the address and the data-word are
written starting with the LSB. To write to each register, a 24-bit
operation is required, as shown in Figure 16. Although many
data-words are fewer than 16 bits wide, all 16 bits must be written
for each register. For example, if the data-word is only eight bits
wide, the upper eight bits are don’t care bits and must be filled
with zeros during the serial write operation. If fewer than 16 data
bits are written, the register is not updated with new data.
Figure 17 shows a more efficient way to write to the registers,
using the ADDI7100 address autoincrement capability. Using
this method, the lowest desired address is written first, followed
by multiple 16-bit data-words. Each data-word is automatically
written to the address of the next highest register. By eliminating
the need to write each address, faster register loading is achieved.
Continuous write operations can start with any register location.
07
60
8
-01
9
A2
SDATA
A0
A1
A4
A5
A6
A7
D0
D1
D2
D3
D13
D14 D15
SL
A3
tLS
8-BIT ADDRESS
16-BIT DATA
24
4
5
6
7
8
9
10
11
12
22
23
tLH
tDH
tDS
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 24 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 16 BITS FOR DATA.
3. IF THE REGISTER LENGTH IS LESS THAN 16 BITS, THEN ZEROS MUST BE USED TO COMPLETE THE 16-BIT
DATA LENGTH.
4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON
THE PARTICULAR REGISTER WRITTEN TO.
SCK
12
3
Figure 16. Serial Write Operation
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
07
60
8-
0
20
SDATA
A0
A1
A2
A6
A7
D0
D1
D14 D15
SCK
SL
A3
D0
D1
D14
D15
D0
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
D2
D1
1
24
23
4
7
89
10
23
26
25
40
39
42
41
43
Figure 17. Continuous Serial Write Operation
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| ADDI7100BCPZRL | 功能描述:IC PROCESSOR CCD SIGNAL7 32LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
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| ADDI9000BCBZRL | 制造商:Analog Devices 功能描述:DRIVER |
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