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參數(shù)資料
| 型號(hào)： | ADCLK854BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:12 48LFCSP |
| 設(shè)計(jì)資源： | Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，CMOS，HSTL，LVDS，LVPECL |
| 輸出： | CMOS，LVDS |
| 頻率 - 最大： | 1.2GHz |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP |
| 包裝： | 托盤 |
ADCLK854
Rev. 0 | Page 14 of 16
APPLICATIONS INFORMATION
USING THE ADCLK854 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed, analog-to-digital converter (ADC) is extremely
sensitive to the quality of the sampling clock provided by the
user. An ADC can be thought of as a sampling mixer, and any
noise, distortion, or timing jitter on the clock is combined with
the desired signal at the analog-to-digital output. Clock integrity
requirements scale with the analog input frequency and resolu-
tion, with higher analog input frequency applications at ≥14-bit
resolution being the most stringent. The theoretical SNR of an
ADC is limited by the ADC resolution and the jitter on the
sampling clock. Considering an ideal ADC of infinite resolution
where the step size and quantization error can be ignored, the
available SNR can be expressed approximately by
×
=
J
AT
f
SNR
2π
1
log
20
where fA is the highest analog frequency being digitized and TJ
is the rms jitter on the sampling clock.
Figure 24 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
For more information, see Application Note AN-756 and
Application Note AN-501 at www.analog.com.
fA FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz)
S
NR
(
d
B
)
EN
O
B
10
1k
100
30
40
50
60
70
80
90
100
110
6
8
10
12
14
16
18
T
J
= 100f
S
200f
S
400f
S
1ps
2ps
10ps
SNR = 20log
1
2πfATJ
07
21
8-
02
4
Figure 24. SNR and ENOB vs. Analog Input Frequency
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.
Consider the input requirements of the ADC (differential or
single-ended, logic level, and termination) when selecting the
best clocking/converter solution.
LVDS CLOCK DISTRIBUTION
The ADCLK854 provides clock outputs that are selectable as
either CMOS or LVDS level outputs. LVDS is a differential
output option that uses a current-mode output stage. The
nominal current is 3.5 mA, which yields 350 mV output swing
across a 100 Ω resistor. The LVDS output meets or exceeds all
ANSI/TIA/EIA-644 specifications. A recommended termination
circuit for the LVDS outputs is shown in Figure 25.
If ac coupling is necessary, place decoupling capacitors either before
or after the 100 Ω termination resistor. See Application Note
AN-586 at www.analog.com for more information on LVDS.
VS
LVDS
100
DIFFERENTIAL (COUPLED)
VS
LVDS
100
0
721
8-
0
25
Figure 25. LVDS Output Termination
CMOS CLOCK DISTRIBUTION
The output drivers of the ADCLK854 can be configured as
CMOS drivers. When selected as a CMOS driver, each output
becomes a pair of CMOS outputs. These outputs are 1.8 V
CMOS compatible.
When single-ended CMOS clocking is used, some of the
following guidelines apply.
Design point-to-point connections such that each driver has only
one receiver, if possible. Connecting outputs in this manner allows
for simple termination schemes and minimizes ringing due to
possible mismatched impedances on the output trace. Series termi-
nation at the source is generally required to provide transmission
line matching and/or to reduce current transients at the driver.
The value of the resistor (typically 10 Ω to 100 Ω) is dependent
on the board design and timing requirements. CMOS outputs
are also limited in terms of the capacitive load or trace length
that they can drive. Typically, trace lengths less than 3 inches are
recommended to preserve signal rise/fall times and signal integrity.
10
MICROSTRIP
60.4
1.0 INCH
CMOS
0
721
8-
0
26
Figure 26. Series Termination of CMOS Output
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the ADCLK854 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far end termination, as shown in Figure 27. The far end
termination network should match the PCB trace impedance and
provide the desired switching point. The reduced signal swing may
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| ADCLK854BCPZ-REEL7 | 功能描述:IC CLOCK BUFFER MUX 2:12 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:- 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ADCLK905 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultrafast SiGe ECL Clock/Data Buffers |
| ADCLK905/PCBZ | 功能描述:BOARD EVAL FOR ADCLK905 16LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| ADCLK905BCPZ-R2 | 功能描述:IC CLK/DATA BUFF DVR 1:1 16LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:SIGe 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
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