參數(shù)資料
型號: ADC1443D160HD
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual channel 14-bit ADC; 160 Msps; JESD204B-compliant CGVxpress? serial outputs
封裝: ADC1443D160HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,;
文件頁數(shù): 38/50頁
文件大小: 408K
代理商: ADC1443D160HD
ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
38 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
[1]
Local register
[1]
Local register
[1]
Local register
[1]
Local register
[1]
Local register
1 to 0
DATA_FORMAT[1:0:]
[1]
R/W
output data format
offset binary
two’s complement
gray code
offset binary
00
01
10
11
Table 26.
Default settings are shown highlighted.
Bit
Symbol
OUTPUT_CFG register (address 0011h) bit description
…continued
Access
Value
Description
Table 27.
Default settings are shown highlighted.
Bit
Symbol
7 to 2
DIG_OFFSET[7:0]
[1]
1 to 0
-
DIG_OFFSET register (address 0013h) bit description
Access
R/W
-
Value
-
-
Description
see
Table 13
not used
Table 28.
Default settings are shown highlighted.
Bit
Symbol
7 to 3
-
2 to 0
TEST_PAT_SEL[2:0]
[1]
TEST_CFG_1 register (address 0014h) bit description
Access
-
R/W
Value
-
-
Description
not used
see
Table 14
Table 29.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
TEST_PAT_USER[13:6]
[1]
TEST_CFG_2 register (address 0015h) bit description
Access
R/W
Value
-
Description
custom digital test pattern (bits 13 to 6)
Table 30.
Default settings are shown highlighted.
Bit
Symbol
7 to 2
TEST_PAT_USER[5:0]
[1]
1 to 0
-
TEST_CFG_3 register (address 0016h) bit description
Access
R/W
-
Value
-
-
Description
custom digital test pattern (bits 7 to 0)
not used
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