參數(shù)資料
型號(hào): ADC1443D160HD
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual channel 14-bit ADC; 160 Msps; JESD204B-compliant CGVxpress? serial outputs
封裝: ADC1443D160HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,;
文件頁(yè)數(shù): 36/50頁(yè)
文件大小: 408K
代理商: ADC1443D160HD
ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
36 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
11.5.3
Detailed register description
The tables in this section contain detailed descriptions of the registers.
11.5.3.1
ADC control registers
[1]
Local register.
Table 20.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
SW_RST
CHIP_RESET register (address 0000h) bit description
Access
R/W
Value
-
Description
resets global and local registers for any value “1”
written at any bit (autoclear).
Table 21.
Default settings are shown highlighted.
Bit
Symbol
7
SW_RST
CHIP_RESET register (address 0005h) bit description
Access
R/W
Value
Description
resets global and local registers
no reset
performs a reset to the default values (autoclear)
not used
0
1
-
6 to 0
-
-
Table 22.
Default settings are shown highlighted.
Bit
Symbol
7 to 2
-
1 to 0
OP_MODE[1:0]
[1]
OP_MODE register (address 0006h) bit description
Access
-
R/W
Value
-
Description
not used
operating mode for the selected channel
normal (power-up)
power-down
sleep
not used
00
01
10
11
Table 23.
Default settings are shown highlighted.
Bit
Symbol
7 to 5
-
4
SE_SEL
CLK_CFG register (address 0007h) bit description
Access
-
R/W
Value
-
Description
not used
single-ended clock input pin selection
CLKP
CLKM
differential/single-ended clock input selection
fully differential
single-ended
0
1
3
DIFF_SE
R/W
0
1
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