參數(shù)資料
型號(hào): ADC1443D160HD
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual channel 14-bit ADC; 160 Msps; JESD204B-compliant CGVxpress? serial outputs
封裝: ADC1443D160HD/C1<SOT935-2 (HLQFN56R)|<<http://www.nxp.com/packages/SOT935-2.html<1<Always Pb-free,;
文件頁(yè)數(shù): 27/50頁(yè)
文件大小: 408K
代理商: ADC1443D160HD
ADC1443D_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 28 September 2011
27 of 50
NXP Semiconductors
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Fig 35. General overview of the JESD204A/JESD204B serializer
FRAME
TO
OCTETS
F octets
SCRAMBLER
TX transport layer
CF: position of control bits
HD: frame boundary break
Padding with Tail bits (TT)
Mx(N'xS) bits
Lx(F) octets
L octets
N' = N+CS
S samples per frame cycle
samples stream to
lane stream mapping
N bits from Cr
+
CS bits for control
N bits from Cr
1
+
CS bits for control
M CONVERTERS
L LANES
LANE 1
FRAME
TO
OCTETS
F octets
SCRAMBLER
8-bit/
10-bit
SER
TX CONTROLLER
LANE 0
8-bit/
10-bit
SER
ALIGNMENT
CHARACTER
GENERATOR
ALIGNMENT
CHARACTER
GENERATOR
SYNC~
005aaa084
Fig 36. Detailed view of the JESD204A/JESD204B serializer with debug functionality
N
AND
CS
N
AND
CS
00
SCR
SCR
PRBS
8-bit/
10-bit
01
00
01
8-bit/
10-bit
PRBS
8
8
N + CS
N + CS
14 + 1
14 + 1
14 + 1
ADC A
PLL
AND
DLL
frame CLK
character CLK
bit CLK
10
10
SER
SER
11
10
00
11
10
00
DUMMY
ADC_PD
ADC_PD
ADC B
PRBS
FSM
(frame
assembly,
character
replication;
ILA,
test mode)
FRAME
ASSEMBLY
aaa-000423
sync_request
14 + 1
ADC_MODE[1:0]
SCR_IN_MODE
SCR_IN_MODE
LANE_MODE[1:0]
LANE_POL
LANE_MODE[1:0]
LANE_POL
14 + 1
14 + 1
DUMMY
PRBS
ADC_MODE[1:0]
×
1
×
F
×
10F
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