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參數(shù)資料
| 型號： | ADC1413S065HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設及接口 |
| 英文描述： | Single 14 bits ADC; 65 Msps; serial JESD204A |
| 封裝： | ADC1413S065HN/C1<SOT1152-1 (HVQFN32R)|<<http://www.nxp.com/packages/SOT1152-1.html<1<Always Pb-free,;ADC1413S065HN/C1<SOT1152-1 (HVQFN32R)|<<http://www.nxp.com/packages/S |
| 文件頁數(shù)： | 19/38頁 |
| 文件大小： | 780K |
| 代理商： | ADC1413S065HN |
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ADC1413S_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 8 June 2011
19 of 38
NXP Semiconductors
ADC1413S series
Single 14-bit ADC: serial JESD204A interface
Single-ended or differential clock inputs can be selected via the SPI (see
Table 20
). If
single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit
SE_SEL.
If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin
should be connected to ground via a capacitor.
11.3.3
Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the input clock signal duty cycle. When the duty cycle stabilizer is active
(bit DCS_EN = logic 1; see
Table 20
), the circuit can handle signals with duty cycles of
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
Table 12.
bit DCS_EN
0
1
11.3.4
Clock input divider
The ADC1413S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV2_SEL = logic 1; see
Table 20
). This feature allows the user to
deliver a higher clock frequency with better jitter performance, leading to a better SNR
result once acquisition has been performed.
11.4 Digital outputs
11.4.1
Serial output equivalent circuit
The JESD204A standard specifies that if the receiver and the transmitter are DC-coupled
both must be fed from the same supply.
The output should be terminated when 100
(typical) is reached at the receiver side.
Duty cycle stabilizer
Description
duty cycle stabilizer disable
duty cycle stabilizer enable
Fig 19. CML output connection to the receiver (DC-coupling)
V
DDD
V
DDD
CMLP
CMLN
AGND
005aaa197
12 mA to 26 mA
100 Ω
+
RECEIVER
50 Ω
50 Ω
-
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1413S065HN/C1,5 | 功能描述:模數(shù)轉換器 - ADC SGL 14b ADC 65MSPS SERIAL JESD204A RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1413S065HN-C1 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN32 - Bulk |
| ADC1413S065HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN32 - Tape and Reel |
| ADC1413S080HN/C1,5 | 功能描述:模數(shù)轉換器 - ADC SGL 14b ADC 80MSPS SERIAL JESD204A RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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