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| 型號(hào)： | ADC1213S065HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Single 12 bits ADC; 65 Msps; serial JESD204A |
| 封裝： | ADC1213S065HN/C1<SOT1152-1 (HVQFN32R)|<<http://www.nxp.com/packages/SOT1152-1.html<1<Always Pb-free,;ADC1213S065HN/C1<SOT1152-1 (HVQFN32R)|<<http://www.nxp.com/packages/S |
| 文件頁(yè)數(shù)： | 29/39頁(yè) |
| 文件大?。?/td> | 719K |
| 代理商： | ADC1213S065HN |
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ADC1213S_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 9 June 2011
29 of 39
NXP Semiconductors
ADC1213S series
Single 12-bit ADC; serial JESD204A interface
11.6.4
JESD204A digital control registers
Table 24.
Default values are highlighted.
Bit
Symbol
7 to 0
TESTPAT_2[11:4]
Register Test pattern 2 (address 0015h)
Access
R/W
Value
00000000 custom digital test pattern (bit 11 to 4)
Description
Table 25.
Default values are highlighted.
Bit
Symbol
7 to 4
TESTPAT_3[3:0]
3 to 0
-
Register Test pattern 3 (address 0016h)
Access
R/W
-
Value
0000
0000
Description
custom digital test pattern (bit 3 to 0)
not used
Table 26.
Default values are highlighted.
Bit
Symbol
7
RXSYNC_ERROR
6 to 4
RESERVED[2:0]
3 to 2
-
1
POR_TST
0
RESERVED
SER_Status (address 0801h)
Access
R
-
-
R
-
Value
0
010
00
0
0
Description
set to 1 when a synchronization error occurs
reserved
not used
power-on-reset
reserved
Table 27.
Default values are highlighted.
Bit
Symbol
7
SW_RST
6 to 4
-
3
FSM_SW_RST
SER_Reset (address 0802h)
Access
R/W
-
R/W
Value
0
000
0
Description
initiates a software reset of the JESD204A unit
not used
initiates a software reset of the internal state machine of
JESD204A unit
not used
2 to 0
-
-
000
Table 28.
Default values are highlighted.
Bit
Symbol
7
-
6
RESERVED
5
SYNC_POL
SER_Control1 (address 0805h)
Access
-
-
R/W
Value
0
0
Description
not used
reserved
defines the synchronization signal polarity:
synchronization signal is active LOW
synchronization signal is active HIGH
defines the input mode of the synchronization signal:
synchronization input mode is set in Differential mode
synchronization input mode is set in Single-ended mode
not used
LSB are swapped to MSB at the scrambler input:
disable
enable
0
1
4
SYNC_SINGLE_ENDED R/W
0
1
1
3
2
-
REV_SCR
-
-
0
1
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| ADC1410S065HN | Single 14-bit ADC 65 Msps CMOS or LVDS DDR digital outputs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1213S065HN/C1,5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SGL 12BIT ADC 65MSPS SERIAL JESD204A RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1213S065HN-C1 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN32 - Bulk |
| ADC1213S065HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN32 - Tape and Reel |
| ADC1213S080C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps serial JESD204A interface |
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