參數(shù)資料
型號(hào): ADC1112D125HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 11-bit ADC; CMOS or LVDS DDR digital outputs
封裝: ADC1112D125HN/C1<SOT804-3|<<<1<Always Pb-free,;ADC1112D125HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 33/41頁
文件大小: 565K
代理商: ADC1112D125HN
ADC1112D125
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 3 March 2011
33 of 41
NXP Semiconductors
ADC1112D125
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
[1]
t
clk
= 1 / f
clk
Table 25.
Default values are highlighted.
Bit
Symbol
7 to 4
-
3
DAVINV
Output clock register (address 0012h) bit description
Access
-
R/W
Value
0000
Description
not used
output clock data valid (DAV) polarity
normal
inverted
DAV phase select
output clock shifted (ahead) by 6/16
×
t
clk
[1]
output clock shifted (ahead) by 5/16
×
t
clk
[1]
output clock shifted (ahead) by 4/16
×
t
clk
[1]
output clock shifted (ahead) by 3/16
×
t
clk
[1]
output clock shifted (ahead) by 2/16
×
t
clk
[1]
output clock shifted (ahead) by 1/16
×
t
clk
[1]
default value as defined in timing section
output clock shifted (delayed) by 1/16
×
t
clk
[1]
0
1
2 to 0
DAVPHASE[2:0]
R/W
000
001
010
011
100
101
110
111
Table 26.
Default values are highlighted.
Bit
Symbol
7 to 6
-
5 to 0
DIG_OFFSET[5:0]
Offset register (address 0013h) bit description
Access
-
R/W
Value
00
Description
not used
digital offset adjustment
+31 LSB
...
0
...
32 LSB
011111
...
000000
...
100000
Table 27.
Default values are highlighted.
Bit
Symbol
7 to 3
-
2 to 0
TESTPAT_SEL[2:0]
Test pattern 1 register (address 0014h) bit description
Access
-
R/W
Value
00000
Description
not used
digital test pattern select
off
mid scale
FS
+FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern
‘0101..0101’
‘1010..1010.’
000
001
010
011
100
101
110
111
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