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參數(shù)資料
| 型號： | ADAV803ASTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 8-Channel 14-Bit Single-Supply Voltage-Output DAC; Package: LQFP (10x10mm); No of Pins: 52; Temperature Range: Industrial |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 35/56頁 |
| 文件大小： | 906K |
| 代理商： | ADAV803ASTZ |
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ADAV803
Table 24. Receiver Configuration 1 Register
NOCL
7
ADDRESS = 0001001 (0x09)
NOCLOCK
Selects the source of the receiver clock when the PLL is not locked.
0 = Recovered PLL clock is used.
1 = ICLK1 is used.
RxCLK1–0
Determines the oversampling ratio of the recovered receiver clock.
00 = RxCLK is a 128 × f
S
recovered clock.
01 = RxCLK is a 256 × f
S
recovered clock.
10 = RxCLK is a 512 × f
11 = Reserved.
AUTO_DEEM
Automatically de-emphasizes the d
0 = Automatic de-emphasis is disabled.
1 = Automatic de-emphasis is enabled.
ERR1–0
Defines what action the receiver
00 = No action is taken.
01 = Last valid sample is held.
10 = Invalid sample is replaced with zeros.
11 = Reserved.
L
Defines what ac
00 = No action is taken.
01 = Last valid sample is held.
10 = Zeros are sent out after the last valid sample.
Rev. 0 | Page 35 of 56
OCK
RxCLK1–
6, 5
AU
4
0
TO_ DEEMPH
ERR1–0
3, 2
LOCK1–0
1, 0
clock.
PH
ata from the receiver based on the channel status information.
should take, if the receiver detects a parity or biphase error.
OCK1–0
tion the receiver should take, if the PLL loses lock.
11 = Soft-mute of the last valid audio sample.
S
recovered
Table 25. Receiver Co
ADDRESS = 0001010 (0x0A)
RxMUTE
SP_PLL
SP_PLL_SEL1–0
NO
ration 2 Register
RxMUTE
7
SP_PL
6
SP_PLL_ SEL
5, 4
RES
3
RES
2
NO NONAUDIO
1
NO_VALIDITY
0
nfigu
L
1–0
Hard-mutes the audio output for the AES3/SPDIF receiver.
0 = AES3/SPDIF receiver is not muted.
1 = AES3/SPDIF receiver is muted.
AES3/SPDIF receiver PLL accepts a left/right clock from one of the four serial ports as the PLL reference clock.
ES3/SPDIF preambles is the reference clock to the PLL.
ports is the reference clock to the PLL.
reference clock to the PLL when SP_PLL is set.
Selects one of the four serial ports as the
00 = Playback port is selected.
01 = Auxiliary input port is selected.
10 = Record port is selected.
11 = Auxiliary output port is selected.
When the NONAUDIO bit is set, data from the AES3/SPDIF receiv
NAUDIO data is due to DTS, AAC, and so on, as d
(SRC). If the NO
the AES3/SPDIF
0 = AES3/SPDIF receiver data is sent to
1 = Data from the AES3/SPDIF receiver i
When the VALIDITY bit is set, data from
NONAUDIO
er is not allowed into the sample rate converter
efined by the IEC61937 standard, then the data from
receiver is not allowed into the SRC regardless of the state of this bit.
the SRC.
s not allowed into the SRC, if the NONAUDIO bit is set.
the AES3/SPDIF receiver is not allowed into the SRC.
0 = AES3/SPDIF receiver data is sent to the SRC.
1 = Data from the AES3/SPDIF receiver is not allowed into the SRC, if the VALIDITY bit is set.
0 = Left/right clock generated from the A
1 = Left/right clock from one of the serial
NO_VALIDITY
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