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參數(shù)資料
型號(hào): ADAU1966WBSTZ
廠商: Analog Devices Inc
文件頁數(shù): 50/52頁
文件大?。?/td> 0K
描述: IC DAC 24BIT SPI/I2C 192K 80LQFP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 24
數(shù)據(jù)接口: I²C,串行,SPI?
轉(zhuǎn)換器數(shù)目: 16
電壓電源: 模擬和數(shù)字
功率耗散(最大): 511mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤
輸出數(shù)目和類型: 16 電壓,單極
采樣率(每秒): *
Data Sheet
ADAU1966
Rev. D | Page 7 of 52
Parameter
Mode
Factor
Min
Typ
Max
Unit
Propagation Delay
48 kHz mode, typical at 48 kHz
25/fS
521
s
96 kHz mode, typical at 96 kHz
11/fS
115
s
192 kHz mode, typical at 192 kHz
8/fS
42
s
192 kHz low delay mode, typical at 192 kHz
2/fS
10
s
TIMING SPECIFICATIONS
40°C < TA < +105°C, DVDD = 2.5 V ± 10%.
Table 7.
Parameter
Description
Min
Typ
Max
Unit
INPUT MASTER CLOCK (MCLK) AND RESET
tMH
MCLK duty cycle, DAC clock source = PLL clock at
256 × fS, 384 × fS, 512 × fS, and 768 × fS
40
60
%
tMH
DAC clock source = direct MCLK at 512 × fS (bypass
on-chip PLL)
40
60
%
fMCLK
MCLKI frequency, PLL mode
6.9
40.5
MHz
fMCLK
Direct MCLK 512 × fS mode
27.1
MHz
fBCLK
DBCLK frequency, PLL mode
27.0
MHz
tPDR
Low
15
ns
tPDRR
Recovery, reset to active output
300
ms
PLL
Lock Time
MCLK input
10
ms
Lock Time
DLRCLK input
50
ms
256 × fS VCO Clock, Output Duty Cycle, MCLKO Pin
40
60
%
SPI PORT
tCCH
CCLK high
35
ns
tCCL
CCLK low
35
ns
fCCLK
CCLK frequency, fCCLK = 1/tCCP; only tCCP shown in Figure 17
10
MHz
tCDS
CDATA setup, time to CCLK rising
10
ns
tCDH
CDATA hold, time from CCLK rising
10
ns
tCLS
CLATCH setup, time to CCLK rising
10
ns
tCLH
CLATCH hold, time from CCLK falling
10
ns
tCLHIGH
CLATCH high, not shown in Figure 17
10
ns
tCOE
COUT enable from CCLK falling
30
ns
tCOD
COUT delay from CCLK falling
30
ns
tCOH
COUT hold from CCLK falling, not shown in Figure 17
30
ns
tCOTS
COUT tristate from CCLK falling
30
ns
I2C
fSCL
SCL clock frequency
400
kHz
tSCLL
SCL low
1.3
s
tSCLH
SCL high
0.6
s
tSCS
Setup time (start condition), relevant for repeated start
condition
0.6
s
tSCH
Hold time (start condition), first clock generated after
this period
0.6
s
tSSH
Setup time (stop condition)
0.6
s
tDS
Data setup time
100
ns
tSR
SDA and SCL rise time
300
ns
tSF
SDA and SCL fall time
300
ns
tBFT
Bus-free time between stop and start
1.3
s
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