參數(shù)資料
型號(hào)： ADAU1961WBCPZ-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 31/76頁(yè)
文件大?。?/td> 0K
描述： IC STEREO AUD CODEC LP 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
類型： 音頻編解碼器
數(shù)據(jù)接口： I²C，串行，SPI?
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 98 / 98
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 96 / 98
電壓 - 電源，模擬： 2.97 V ~ 3.63 V
電壓 - 電源，數(shù)字： 2.97 V ~ 3.63 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-EP（5x5）
包裝： 帶卷 (TR)
Data Sheet
ADAU1961
Rev. A | Page 37 of 76
The R/W bit determines the direction of the data. A Logic 0 on
the LSB of the first byte means that the master will write infor-
mation to the peripheral, whereas a Logic 1 means that the
master will read information from the peripheral after writing
the subaddress and repeating the start address. A data transfer
takes place until a stop condition is encountered. A stop
condition occurs when SDA transitions from low to high while
SCL is held high. Figure 48 shows the timing of an I2C write,
and Figure 49 shows an I2C read.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the ADAU1961 immediately
jumps to the idle condition. During a given SCL high period,
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADAU1961 does
not issue an acknowledge and returns to the idle condition.
If the user exceeds the highest subaddress while in autoincrement
mode, one of two actions is taken. In read mode, the ADAU1961
outputs the highest subaddress register contents until the master
device issues a no acknowledge, indicating the end of a read. A
no acknowledge condition is where the SDA line is not pulled
low on the ninth clock pulse on SCL. If the highest subaddress
location is reached while in write mode, the data for the invalid
byte is not loaded into any subaddress register, a no acknowledge
is issued by the ADAU1961, and the part returns to the idle
condition.
R/W
0
SCL
SDA
(CONTINUED)
SCL
(CONTINUED)
11
1
ADDR0
ADDR1
0
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
DATA BYTE 1
ACK BY
ADAU1961
ACK BY
ADAU1961
ACK BY
ADAU1961
ACK BY
ADAU1961
STOP BY
MASTER
08
915
-03
2
Figure 48. I2C Write to ADAU1961 Clocking
R/W
SCL
SDA
(CONTINUED)
SCL
(CONTINUED)
SDA
(CONTINUED)
SCL
(CONTINUED)
START BY
MASTER
FRAME 2
SUBADDRESS BYTE 1
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
CHIP ADDRESS BYTE
FRAME 1
CHIP ADDRESS BYTE
FRAME 5
READ DATA BYTE 1
ACK BY
ADAU1961
ACK BY
ADAU1961
ACK BY
ADAU1961
ACK BY
ADAU1961
STOP BY
MASTER
ACK BY
MASTER
REPEATED
START BY MASTER
R/W
ADDR0
ADDR1
01
1
0
01
1
0
0
89
15
-03
3
Figure 49. I2C Read from ADAU1961 Clocking
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