參數(shù)資料
型號(hào)： ADAU1461WBCPZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 37/88頁(yè)
文件大小： 0K
描述： IC SIGMADSP 24BIT 96KHZ PLL 32
標(biāo)準(zhǔn)包裝： 5,000
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 車(chē)載音頻
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
ADAU1461
Rev. 0 | Page 42 of 88
APPLICATIONS INFORMATION
POWER SUPPLY BYPASS CAPACITORS
Each analog and digital power supply pin should be bypassed to
its nearest appropriate ground pin with a single 100 nF capaci-
tor. The connections to each side of the capacitor should be as
short as possible, and the trace should stay on a single layer with
no vias. For maximum effectiveness, locate the capacitor equi-
distant from the power and ground pins or, when equidistant
placement is not possible, slightly closer to the power pin.
Thermal connections to the ground planes should be made
on the far side of the capacitor.
Each supply signal on the board should also be bypassed with a
single bulk capacitor (10 μF to 47 μF).
VDD
GND
TO VDD
CAPACITOR
TO GND
08
91
4-
0
48
Figure 63. Recommended Power Supply Bypass Capacitor Layout
GSM NOISE FILTER
In mobile phone applications, excessive 217 Hz GSM noise on
the analog supply pins can degrade the audio quality. To avoid
this problem, it is recommended that an L-C filter be used in
series with the bypass capacitors for the AVDD pins. This filter
should consist of a 1.2 nH inductor and a 9.1 pF capacitor in
series between AVDD and ground, as shown in Figure 64.
AVDD
0.1F
9.1pF
1.2nH
10F
+
0
89
14
-0
TOP
POWER
GROUND
BOTTOM
COPPER SQUARES
VIAS
49
Figure 64. GSM Filter on the Analog Supply Pins
GROUNDING
A single ground plane should be used in the application layout.
Components in an analog signal path should be placed away
from digital signals.
EXPOSED PAD PCB DESIGN
The ADAU1461 has an exposed pad on the underside of the
LFCSP. This pad is used to couple the package to the PCB for
heat dissipation when using the outputs to drive earpiece or
headphone loads. When designing a board for the ADAU1461,
special consideration should be given to the following:
A copper layer equal in size to the exposed pad should be
on all layers of the board, from top to bottom, and should
connect somewhere to a dedicated copper board layer (see
Vias should be placed to connect all layers of copper,
allowing for efficient heat and energy conductivity. For an
example, see Figure 66, which has nine vias arranged in a
3 inch × 3 inch grid in the pad area.
89
14
-0
50
0
Figure 65. Exposed Pad Layout Example, Side View
08
91
4-
0
51
Figure 66. Exposed Pad Layout Example, Top View
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