參數(shù)資料
型號： ADAU1401YSTZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 5/52頁
文件大?。?/td> 0K
描述： IC AUDIO PROC 28/56BIT 48LQFP
標準包裝： 2,000
系列： SigmaDSP®
類型： 音頻處理器
應用： 監(jiān)控器，電視
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應商設備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
Data Sheet
ADAU1401
Rev. C | Page 13 of 52
Pin No.
Mnemonic
Type1
Description
13, 24
DVDD
PWR
1.8 V Digital Supply. This can be supplied either externally or generated from a 3.3 V
supply with the on-board 1.8 V regulator. DVDD should be decoupled to DGND with a
100 nF capacitor.
14
MP7
D_IO
Multipurpose GPIO or Serial Output Port Data 1 (SDATA_OUT1). See the Multipurpose Pins
section for more details.
15
MP6
D_IO
Multipurpose GPIO, Serial Output Port Data 0, or TDM Data Output (SDATA_OUT0). See the
Multipurpose Pins section for more details.
16
MP10
D_IO
Multipurpose GPIO or Serial Output Port LRCLK (OUTPUT_LRCLK). See the Multipurpose
Pins section for more details.
17
VDRIVE
A_OUT
Drive for 1.8 V Regulator. The base of the voltage regulator external PNP transistor is
driven from VDRIVE. See the Voltage Regulator section for details.
18
IOVDD
PWR
Supply for Input and Output Pins. The voltage on this pin sets the highest input voltage
that should be seen on the digital input pins. This pin is also the supply for the digital
output signals on the control port and MP pins. IOVDD should always be set to 3.3 V. The
current draw of this pin is variable because it is dependent on the loads of the digital
outputs.
19
MP11
D_IO
Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK). See the Multipurpose Pins
section for more details.
20
ADDR1/CDATA/WB
D_IN
ADDR1: I2C Address 1. In combination with ADDR0, this sets the I2C address of the IC so
that four ADAU1401s can be used on the same I2C bus. See the I2C Port section for details.
CDATA: SPI Data Input. See the SPI Port section for details.
WB: EEPROM Writeback Trigger. A rising (default) or falling (if set in the EEPROM messages)
edge on this pin triggers a writeback of the interface registers to the external EEPROM.
This function can be used to save parameter data on power-down. See the Self-Boot
section for details.
21
CLATCH/WP
D_IO
CLATCH: SPI Latch Signal. Must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction can take a different number of cycles on the CCLK
pin to complete, depending on the address and read/write bit that are sent at the
beginning of the SPI transaction. See the SPI Port section for details.
WP: Self-Boot EEPROM Write Protect. This pin is an open-collector output when in self-
boot mode. The ADAU1401 pulls this low to enable writes to an external EEPROM. This pin
should be pulled high to 3.3 V. See the Self-Boot section for details.
22
SDA/COUT
D_IO
SDA: I2C Data. This pin is a bidirectional open-collector. The line connected to this pin
should have a 2.2 kΩ pull-up resistor. See the I2C Port section for details.
COUT: This SPI data output is used for reading back registers and memory locations. It is
three-stated when an SPI read is not active. See the SPI Port section for details.
23
SCL/CCLK
D_IO
SCL: I2C Clock. This pin is always an open-collector input when in I2C control mode. In self-
boot mode, this pin is an open-collector output (I2C master). The line connected to this pin
should have a 2.2 kΩ pull-up resistor. See the I2C Port section for details.
CCLK: SPI Clock. This pin can either run continuously or be gated off between SPI
transactions. See the SPI Port section for details.
26
MP9
D_IO/A_IO
Multipurpose GPIO, Serial Output Port Data 3 (SDATA_OUT3), or Auxiliary ADC Input 0. See
the Multipurpose Pins section for more details.
27
MP8
D_IO/A_IO
Multipurpose GPIO, Serial Output Port Data 2 (SDATA_OUT2), or Auxiliary ADC Input 3. See
the Multipurpose Pins section for more details.
28
MP3
D_IO/A_IO
Multipurpose GPIO, Serial Input Port Data 3 (SDATA_IN3), or Auxiliary
ADC Input 2. See the Multipurpose Pins section for more details.
29
MP2
D_IO/A_IO
Multipurpose GPIO, Serial Input Port Data 2 (SDATA_IN2), or Auxiliary
ADC Input 1. See the Multipurpose Pins section for more details.
30
RSVD
X
Reserved. Tie to ground, either directly or through a pull-down resistor.
31
OSCO
D_OUT
Crystal Oscillator Circuit Output. A 100 Ω damping resistor should be connected between
this pin and the crystal. This output should not be used to directly drive a clock to another
IC. If the crystal oscillator is not used, this pin can be left disconnected. See the Using the
Oscillator section for details.
32
MCLKI
D_IN
Master Clock Input. MCLKI can either be connected to a 3.3 V clock signal or be the input
from the crystal oscillator circuit. See the Setting Master Clock/PLL Mode section for
details.
33
PGND
PWR
PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly together in a
common ground plane. PGND should be decoupled to PVDD with a 100 nF capacitor.
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