I2C Read and Write Operations Figure " />
參數(shù)資料
型號： ADAU1401YSTZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 19/52頁
文件大小： 0K
描述： IC AUDIO PROC 28/56BIT 48LQFP
標準包裝： 2,000
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 監(jiān)控器，電視
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
ADAU1401
Data Sheet
Rev. C | Page 26 of 52
I2C Read and Write Operations
Figure 22 shows the timing of a single-word write operation.
Every ninth clock, the ADAU1401 issues an acknowledge by
pulling SDA low.
Figure 23 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The ADAU1401 knows to increment its
subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
2-byte word length.
The timing of a single-word read operation is shown in
Figure 24. Note that the first R/W bit is 0, indicating a write
operation. This is because the subaddress still needs to be
written to set up the internal address. After the ADAU1401
acknowledges the receipt of the subaddress, the master must
issue a repeated start command followed by the chip address
byte with the R/W set to 1 (read). This causes the ADAU1401
SDA to reverse and begin driving data back to the master. The
master then responds every ninth pulse with an acknowledge
pulse to the ADAU1401.
Figure 25 shows the timing of a burst mode read sequence. This
figure shows an example where the target read registers are two
bytes. The ADAU1401 increments its subaddress every two bytes
because the requested subaddress corresponds to a register or
memory area with word lengths of two bytes. Other addresses
may have word lengths ranging from one to five bytes. The
ADAU1401 always decodes the subaddress and sets the auto-
increment circuit so that the address increments after the
appropriate number of bytes.
Figure 22 to Figure 25 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
S
AS
SUBADDRESS
LOW
DATA BYTE 1
DATA BYTE 2
AS
P
DATA BYTE N
SUBADDRESS
HIGH
CHIP ADDRESS,
R/W = 0
067
52-
02
2
Figure 22. Single Word I2C Write Format
S
AS
SUBADDRESS
LOW
DATA-
WORD 1,
BYTE 1
DATA-
WORD 1,
BYTE 2
DATA-
WORD 2,
BYTE 1
DATA-
WORD 2,
BYTE 2
AS
P
SUBADDRESS
HIGH
CHIP ADDRESS,
R/W = 0
06
75
2-
02
3
Figure 23. Burst Mode I2C Write Format
06
75
2-
0
24
S
AS
S
SUBADDRESS
LOW
AM
AS
DATA
BYTE 1
DATA
BYTE 2
DATA
BYTE N
P
SUBADDRESS
HIGH
CHIP ADDRESS,
R/W = 0
CHIP ADDRESS,
R/W = 1
Figure 24. Single-Word I2C Read Format
06
752
-0
25
S
AS
S
SUBADDRESS
LOW
AM
AS
DATA-
WORD 1,
BYTE 1
AM
DATA-
WORD 1,
BYTE 2
P
SUBADDRESS
HIGH
CHIP ADDRESS,
R/W = 0
CHIP ADDRESS,
R/W = 1
Figure 25. Burst Mode I2C Read Format
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