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參數(shù)資料
| 型號： | ADATE207BBP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Quad Pin Timing Formatter |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | MO-192-BAL-2, LBGA-256 |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 374K |
| 代理商： | ADATE207BBP |
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ADATE207
Name:
Address:
Type:
Rev. 0 | Page 23 of 36
Fail Counter High
0x02
Read/Write
Table 16. Fail Counter High
Position
Bits[15:00]
Description
Fail Counter Data High. This field contains the 16 MSBs of the fail counter. See Table 15, the fail
counter low register, for more information.
Reset State
0x0000
Name:
Address:
Type:
Static Configuration
0x03
Read/Write
Table 17. Static Configuration
Position
Bits[15:04]
Bit 03
Description
Not Used.
Ch_Data_Low.
A high with edges disabled produces a low level output from the drive data (DR_DATA) signal
regardless of pattern data.
Pulsing this bit allows the data to be preset to a low level output prior to bursting a pattern.
Control of the drive data is pattern data dependent when a pattern is burst.
If both Data_High and Data_Low are high, the data is indeterminate.
Ch_Data_High.
A high with edges disabled produces a high level output from the drive data (DR_DATA) signal
regardless of pattern data
Pulsing this bit allows the data to be preset to a high level output prior to bursting a pattern.
Control of the drive data is pattern data dependent when a pattern is burst.
Ch_Driver_Off.
A high with edges disabled produces a low level output from the drive enable (DR_EN) signal,
tristating the driver regardless of pattern data.
Pulsing this bit allows the driver to tristate prior to bursting a pattern.
Control of the driver is pattern data dependent when a pattern is burst.
If both Driver_On and Driver_Off are high, the drive enable signal (DR_EN) is indeterminate.
Ch_Driver_On.
A high with edges disabled produces high level output from the drive enable (DR_EN) signal,
enabling the driver regardless of pattern data.
Pulsing this bit enables the driver prior to bursting a pattern.
Control of the driver is pattern data dependent when a pattern is burst.
Reset State
0x000
0
Bit 02
0
Bit 01
0
Bit 00
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADATE207BBPZ | 功能描述:IC TIMING FORMATTER QUAD 256BGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| ADATE209 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4.0 Gbps Dual Driver |
| ADATE209BBCZ | 制造商:Analog Devices 功能描述:4.0 GBPS DUAL DRIVER - Rail/Tube |
| ADATE209BCPZ | 制造商:Analog Devices 功能描述: |
| ADATE302-02 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MHz Dual Integrated DCL with Differential Drive/Receive, Level Setting DACs, and Per Pin PMU |
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