參數(shù)資料
型號: AD9995
廠商: Analog Devices, Inc.
英文描述: 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator
中文描述: 12位CCD信號處理器與精密計時⑩發(fā)生器
文件頁數(shù): 50/60頁
文件大?。?/td> 1593K
代理商: AD9995
AD9995
–50–
Table XXXVIII. V-Sequence 1 (VSEQ1) Register Map
Data Bit Default
Address Content
88
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register Name
HBLKMASK_1
CLPOBPOL_1
PBLKPOL_1
VPATSEL_1
VMASK_1
HBLKALT_1
UNUSED
VPATREPO_1
VPATREPE_1
VPATSTART_1
HDLEN_1
PBLKTOG1_1
PBLKTOG2_1
HBLKTOG1_1
HBLKTOG2_1
HBLKTOG3_1
HBLKTOG4_1
HBLKTOG5_1
HBLKTOG6_1
CLPOBTOG1_1
CLPOBTOG2_1
Description
Masking Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
Selected V-Pattern Group for V-Sequence 1
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
Enable HBLK Alternation
Unused
Number of Selected V-Pattern Group Repetitions for Odd Lines
Number of Selected V-Pattern Group Repetitions for Even Lines
Start Position in the Line for the Selected V-Pattern Group
HD Line Length (Number of Pixels) for V-Sequence 1
PBLK Toggle Position 1 for V-Sequence 1
PBLK Toggle Position 2 for V-Sequence 1
HBLK Toggle Position 1 for V-Sequence 1
HBLK Toggle Position 2 for V-Sequence 1
HBLK Toggle Position 3 for V-Sequence 1
HBLK Toggle Position 4 for V-Sequence 1
HBLK Toggle Position 5 for V-Sequence 1
HBLK Toggle Position 6 for V-Sequence 1
CLPOB Toggle Position 1 for V-Sequence 1
CLPOB Toggle Position 2 for V-Sequence 1
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
89
8A
8B
8C
8D
8E
8F
Table XXXIX. V-Sequence 2 (VSEQ2) Register Map
Data Bit Default
Address Content
90
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register Name
HBLKMASK_2
CLPOBPOL_2
PBLKPOL_2
VPATSEL_2
VMASK_2
HBLKALT_2
UNUSED
VPATREPO_2
VPATREPE_2
VPATSTART_2
HDLEN_2
PBLKTOG1_2
PBLKTOG2_2
HBLKTOG1_2
HBLKTOG2_2
HBLKTOG3_2
HBLKTOG4_2
HBLKTOG5_2
HBLKTOG6_2
CLPOBTOG1_2
CLPOBTOG2_2
Description
Masking Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
Selected V-Pattern Group for V-Sequence 2
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
Enable HBLK Alternation
Unused
Number of Selected V-Pattern Group Repetitions for Odd Lines
Number of Selected V-Pattern Group Repetitions for Even Lines
Start Position in the Line for the Selected V-Pattern Group
HD Line Length (Number of Pixels) for V-Sequence 2
PBLK Toggle Position 1 for V-Sequence 2
PBLK Toggle Position 2 for V-Sequence 2
HBLK Toggle Position 1 for V-Sequence 2
HBLK Toggle Position 2 for V-Sequence 2
HBLK Toggle Position 3 for V-Sequence 2
HBLK Toggle Position 4 for V-Sequence 2
HBLK Toggle Position 5 for V-Sequence 2
HBLK Toggle Position 6 for V-Sequence 2
CLPOB Toggle Position 1 for V-Sequence 2
CLPOB Toggle Position 2 for V-Sequence 2
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
91
92
93
94
95
96
97
REV. 0
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