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參數(shù)資料
| 型號(hào)： | AD9995 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator |
| 中文描述： | 12位CCD信號(hào)處理器與精密計(jì)時(shí)⑩發(fā)生器 |
| 文件頁(yè)數(shù)： | 42/60頁(yè) |
| 文件大?。?/td> | 1593K |
| 代理商： | AD9995 |
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AD9995
–42–
Table XXII. Shutter Control Register Map (continued)
Data Bit Default
Address Content
67
68
69
6A
6B
6C
6D
6E
6F
70
71
Value
0
1000
1
0
0
0
1
0
0
0
0
Register Name
VSUBMODE
VSUBON
MSHUTPOL
MSHUTON
MSHUTOFF_FD
MSHUTOFF_LNPX
STROBPOL
STROBON_FD
STROBON_LNPX
STROBOFF_FD
STROBOFF_LNPX
Register Description
VSUB Readout Mode [0]. VSUB Keep-On Mode [1].
VSUB ON Position [11:0]. VSUB Active Polarity [12].
MSHUT Active Polarity [0]. MSHUT Manual Enable [1].
MSHUT ON Position. Line [11:0]. Pixel [23:0].
MSHUT OFF Field Position.
MSHUT OFF Position. Line [11:0]. Pixel [23:12].
STROBE Active Polarity.
STROBE ON Field Position.
STROBE ON Position. Line [11:0]. Pixel [23:12].
STROBE OFF Field Position.
STROBE OFF Position. Line [11:0]. Pixel [23:12].
[1:0]
[12:0]
[1:0]
[23:0]
[11:0]
[23:0]
[0]
[11:0]
[23:0]
[11:0]
[23:0]
Table XXIII. Register Map Selection
Data Bit Default
Address Content
7F
Value
0
Register Name
BANKSELECT1
Register Description
Register Bank Access from Bank 1 to Bank 2. 0 = Bank 1, 1 = Bank 2.
[0]
Table XXIV. AFE Operation Register Detail
Data Bit Default
Address Content
00
Value
3
1
0
0
0
0
0
0
Register Name
PWRDOWN
CLPENABLE
CLPSPEED
TEST
PBLK_LVL
TEST
DCBYP
TEST
Register Description
0 = Normal Operation, 1 = Standby 1, 2 = Standby 2, 3 = Standby 3.
0 = Disable OB Clamp, 1 = Enable OB Clamp.
0 = Select Normal OB Clamp Settling, 1 = Select Fast OB Clamp Settling.
Test Use Only. Set to 0.
DOUT Value during PBLK: 0 = Blank to Zero, 1 = Blank to Clamp Level.
Test Use Only. Set to 0.
0 = Enable DC Restore Circuit, 1 = Bypass DC Restore Circuit during PBLK.
Test Use Only. Set to 0.
[1:0]
[2]
[3]
[4]
[5]
[7:6]
[8]
[9]
Table XXV. AFE Control Register Detail
Data Bit Default
Address Content
03
Value
0
1
0
0
0
Register Name
TEST
TEST
DOUTDISABLE
DOUTLATCH
GRAYENCODE
Register Description
Test Use Only. Set to 00.
Test Use Only. Set to 1.
0 = Data Outputs are Driven, 1 = Data Outputs are Three-Stated.
0 = Latch Data Outputs with DOUT Phase, 1 = Output Latch Transparent.
0 = Binary Encode Data Outputs, 1 = Gray Encode Data Outputs.
[1:0]
[2]
[3]
[4]
[5]
REV. 0
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| AD9995KCPZRL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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