參數(shù)資料
型號： AD9991
廠商： Analog Devices, Inc.
英文描述： 10-Bit CCD Signal Processor with Precision Timing Generator
中文描述： 10位CCD信號處理器與精密時序發(fā)生器
文件頁數(shù)： 49/60頁
文件大?。?/td> 826K
代理商： AD9991
AD9991
–49–
Table XXXV. V-Pattern Group 9 (VPAT9) Register Map (continued)
Data Bit Default
Address Content Value Register Name Description
79 [11:0] 0 V6TOG1_9 V5 Toggle Position 1
[23:12] 0 V6TOG2_9 V5 Toggle Position 2
7A [11:0] 0 V6TOG3_9 V5 Toggle Position 3
[23:12] 0 V6TOG4_9 V5 Toggle Position 4
7B [11:0] 0 V6TOG1_9 V6 Toggle Position 1
[23:12] 0 V6TOG2_9 V6 Toggle Position 2
7C [11:0] 0 V6TOG3_9 V6 Toggle Position 3
[23:12] 0 V6TOG4_9 V6 Toggle Position 4
7D [11:0] 0 FREEZE1_9 V1–V6 Freeze Position 1
[23:12] 0 RESUME1_9 V1–V6 Resume Position 1
7E [11:0] 0 FREEZE2_9 V1–V6 Freeze Position 2
[23:12] 0 RESUME2_9 V1–V6 Resume Position 2
Table XXXVI. Register Map Selection (SCK Updated Register)
Data Bit Default
Address Content Value Register Name Register Description
7F [0] 0 BANKSELECT2 Register Bank Access from Bank 2 to Bank 1. 0 = Bank 1, 1 = Bank 2.
Table XXXVII. V-Sequence 0 (VSEQ0) Register Map
Data Bit Default
Address Content Value Register Name Description
80 [1:0] 0 HBLKMASK_0 Masking Polarity during HBLK. H1 [0]. H3 [1].
[2] 0 CLPOBPOL_0 CLPOB Start Polarity
[3] 0 PBLKPOL_0 PBLK Start Polarity
[7:4] 0 VPATSEL_0 Selected V-Pattern Group for V-Sequence 0
[9:8] 0 VMASK_0 Enable Masking of V-Outputs (Specified by Freeze/Resume Registers)
[11:10] 0 HBLKALT_0 Enable HBLK Alternation
[23:12] 0 UNUSED Unused
81 [11:0] 0 VPATREPO_0 Number of Selected V-Pattern Group Repetitions for Odd Lines
[23:12] 0 VPATREPE_0 Number of Selected V-Pattern Group Repetitions for Even Lines
82 [11:0] 0 VPATSTART_0 Start Position in the Line for the Selected V-Pattern Group
[23:12] 0 HDLEN_0 HD Line Length (Number of Pixels) for V-Sequence 0
83 [11:0] 0 PBLKTOG1_0 PBLK Toggle Position 1 for V-Sequence 0
[23:12] 0 PBLKTOG2_0 PBLK Toggle Position 2 for V-Sequence 0
84 [11:0] 0 HBLKTOG1_0 HBLK Toggle Position 1 for V-Sequence 0
[23:12] 0 HBLKTOG2_0 HBLK Toggle Position 2 for V-Sequence 0
85 [11:0] 0 HBLKTOG3_0 HBLK Toggle Position 3 for V-Sequence 0
[23:12] 0 HBLKTOG4_0 HBLK Toggle Position 4 for V-Sequence 0
86 [11:0] 0 HBLKTOG5_0 HBLK Toggle Position 5 for V-Sequence 0
[23:12] 0 HBLKTOG6_0 HBLK Toggle Position 6 for V-Sequence 0
87 [11:0] 0 CLPOBTOG1_0 CLPOB Toggle Position 1 for V-Sequence 0
[23:12] 0 CLPOBTOG2_0 CLPOB Toggle Position 2 for V-Sequence 0
REV. 0
相關(guān)PDF資料
PDF描述
AD9992 12-Bit CCD Signal Processor with Precision Timing Generator
AD9992BBCZ 12-Bit CCD Signal Processor with Precision Timing Generator
AD9992BBCZRL 12-Bit CCD Signal Processor with Precision Timing Generator
AD9995KCP 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator
AD9995KCPRL 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9991KCP 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 56-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD9991KCPRL 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 56-Pin LFCSP EP T/R
AD9991KCPZ 功能描述:IC CCD SIGNAL PROCESSOR 56-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件
AD9991KCPZRL 功能描述:IC CCD SIGNAL PROCESSOR 56-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件
AD9992 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator
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