參數(shù)資料
型號: AD9991
廠商: Analog Devices, Inc.
英文描述: 10-Bit CCD Signal Processor with Precision Timing Generator
中文描述: 10位CCD信號處理器與精密時(shí)序發(fā)生器
文件頁數(shù): 12/60頁
文件大?。?/td> 826K
代理商: AD9991
AD9991
–12–
P[0]
PIXEL
PERIOD
RG
H1/H3
RGf[12]
P[48] = P[0]
Hf[24]
CCD
SIGNAL
P[24]
P[12]
P[36]
Hr[0]
RGr[0]
SHD[0]
NOTES
ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.
DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.
POSITION
t
S1
H2/H4
SHP[24]
Figure 7. High Speed Timing Default Locations
NOTES
DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.
OUTPUT DELAY (
t
OD
) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.
P[0]
P[48] = P[0]
PIXEL
PERIOD
P[12]
P[24]
P[36]
DOUT
DCLK
t
OD
Figure 8a. Digital Output Phase Adjustment
NOTES
DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0, DCLKMODE = 0.
HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
DCLK
DOUT
CCDIN
CLI
SHD
(INTERNAL)
N
N+1
N+2
N+12
N+11
N+10
N+9
N+8
N+7
N+6
N+5
N+4
N+3
N+13
N-13
N-3
N-4
N-5
N-6
N-7
N-8
N-9
N-10
N-11
N-12
N-2
N-1
N+1
N
SAMPLE PIXEL N
PIPELINE LATENCY=11 CYCLES
t
CLIDLY
N-1
N+2
Figure 8b. Pipeline Delay
REV. 0
相關(guān)PDF資料
PDF描述
AD9992 12-Bit CCD Signal Processor with Precision Timing Generator
AD9992BBCZ 12-Bit CCD Signal Processor with Precision Timing Generator
AD9992BBCZRL 12-Bit CCD Signal Processor with Precision Timing Generator
AD9995KCP 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator
AD9995KCPRL 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator
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AD9992 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator