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參數資料
| 型號： | AD9991 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | 10位CCD信號處理器與精密時序發(fā)生器 |
| 文件頁數： | 16/60頁 |
| 文件大小： | 826K |
| 代理商： | AD9991 |
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AD9991
–16–
VERTICAL TIMING GENERATION
The AD9991 provides a very flexible solution for generating
vertical CCD timing, and can support multiple CCDs and dif-
ferent system architectures. The 6-phase vertical transfer clocks
V1–V6 are used to shift each line of pixels into the horizontal
output register of the CCD. The AD9991 allows these outputs to
be individually programmed into various readout configurations
using a four step process.
Figure 15 shows an overview of how the vertical timing is gener-
ated in four steps. First, the individual pulse patterns for V1–V6
are created by using the vertical pattern group registers. Second,
the V-pattern groups are used to build the sequences, where
additional information is added. Third, the readout for an entire
field is constructed by dividing the field into different regions and
then assigning a sequence to each region. Each field can contain
up to seven different regions to accommodate different steps of
the readout such as high speed line shifts and unique vertical line
transfers. Up to six different fields may be created. Finally, the
Mode register allows the different fields to be combined into any
order for various readout configurations.
REGREGREGION 0: USE V-SEQUENCE 3
REGION 1: USE V-SEQUENCE 2
REGION 2: USE V-SEQUENCE 1
REGREGION 0: USE V-SEQUENCE 3
REGION 2: USE V-SEQUENCE 1
REGION 0: USE V-SEQUENCE 2
REGION 3: USE V-SEQUENCE 0
REGION 4: USE V-SEQUENCE 2
CREATE THE VERTICAL PATTERN GROUPS
(MAXIMUM OF 10 GROUPS).
BUILD THE V-SEQUENCES BY ADDING LINE START
POSITION, # OF REPEATS, AND HBLK/CLPOB PULSES
(MAXIMUM OF 10 V-SEQUENCES).
V-SEQUENCE 0
(VPAT0, 1 REP)
BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS,
AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH
(MAXIMUM OF 7 REGIONS IN EACH FIELD)
(MAXIMUM OF 6 FIELDS).
FIELD 0
V1
V2
V5
V6
V1
V2
V3
V4
FIELD 1
FIELD 2
USE THE MODE REGISTER TO CONTROL WHICH FIELDS
ARE USED, AND IN WHAT ORDER
(MAXIMUM OF 7 FIELDS MAY BE COMBINED IN ANY ORDER).
FIELD 0
FIELD 1
FIELD 2
FIELD 3
FIELD 4
FIELD 5
FIELD 1
FIELD 4
FIELD 2
V4
V3
V5
V6
V-SEQUENCE 1
(VPAT9, 2 REP)
V-SEQUENCE 2
(VPAT9, N REP)
VPAT 0
V1
V2
V5
V6
V4
V3
V1
V2
V5
V6
V4
V3
V1
V2
V5
V6
V4
V3
VPAT 9
Figure 15. Summary of Vertical Timing Generation
REV. 0
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| AD9991KCPZRL | 功能描述:IC CCD SIGNAL PROCESSOR 56-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9992 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
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