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| 型號： | AD9984AKCPZ-170 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DISPLAY 10BIT 170MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 接口 |
| 應(yīng)用： | 顯示器，處理，電視 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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AD9984A
Rev. 0 | Page 30 of 44
2-WIRE SERIAL CONTROL REGISTERS
CHIP IDENTIFICATION
0x00—Bits[7:0] Chip Revision
This is an 8-bit register that represents the silicon revision.
PLL DIVIDER CONTROL
0x01—Bits[7:0] PLL Divide Ratio MSBs
These are the 8 MSBs of the 12-bit PLL divide ratio (PLLDIV).
The PLL derives a pixel clock from the incoming Hsync signal.
The pixel clock frequency is then divided by an integer value,
such that the output is phase-locked to Hsync. This PLLDIV
value determines the number of pixel times (pixels plus
horizontal blanking overhead) per line. This is typically 20% to
30% more than the number of active pixels in the display.
The 12-bit value of the PLL divider supports divide ratios from
2 to 4095 as long as the output frequency is within range. The
higher the value loaded in this register, the higher the resulting
clock frequency with respect to a fixed Hsync frequency.
VESA has established some standard timing specifications that
assist in determining the value for PLLDIV as a function of
horizontal and vertical display resolution and frame rate (see
Table 10). However, many computer systems do not precisely
conform to the recommendations. As a result, these numbers
should be used only as a guide. The display system manufac-
turer should provide automatic or manual means for optimizing
PLLDIV. An incorrectly set PLLDIV usually produces one or
more vertical noise bars on the display. The greater the error,
the greater the number of bars produced.
The power-up default value of PLLDIV is 1693.
PLLDIVM = 0x69, PLLDIVL = 0xDX.
The AD9984A updates the full divide ratio only when the LSBs are
written. Writing to this register by itself does not trigger an update.
0x02—Bits[7:4] PLL Divide Ratio LSBs
These are the four LSBs of the 12-bit PLL divide ratio (PLLDIV).
The power-up default value of PLLDIV is 1693. PLLDIVM = 0x69,
PLLDIVL = 0xDX.
CLOCK GENERATOR CONTROL
0x03—Bits[7:6] VCO Range Select
These two bits establish the operating range of the clock
generator. VCO range must be set to correspond to the desired
operating frequency (incoming pixel rate). The PLL gives the
best jitter performance at high frequencies. For this reason, to
output low pixel rates and still achieve good jitter performance,
the PLL operates at a higher frequency, but then divides down
the clock rate afterwards. See Table 15 for the pixel rates of each
VCO range setting. The PLL output divisor is automatically
selected with the VCO range setting. The power-up default
value is 01.
Table 15. VCO Range Select Bits
Value
Result (Pixel Rates)
00
10 to 31
01
31 to 62
10
62 to 124
11
124 to 170
0x03—Bits[5:3] Charge Pump Current
These three bits establish the current driving the loop filter in
the clock generator. The current must be set to correspond with
the desired operating frequency. The power-up default value is
current = 001.
Table 16. Charge Pump Current Bits
Ip2
Ip1
Ip0
Result (Current)
0
50
0
1
100
0
1
0
150
0
1
250
1
0
350
1
0
1
500
1
0
750
1
1500
0x03—Bit[2] External Clock Enable
This bit determines the source of the pixel clock.
Table 17. External Clock Enable Bit
Value
Result
0
Internally generated clock.
1
Externally provided clock signal.
A Logic 0 enables the internal PLL that generates the pixel clock
from an externally provided Hsync.
A Logic 1 enables the external EXTCK input pin. In this mode,
the PLL divide ratio (PLLDIV) is ignored. The clock phase
adjust (Phase) is still functional. The power-up default value is
EXTCK = 0.
PHASE ADJUST
0x04—Bits[7:3] ADC Clock Phase Adjust
These bits adjust the phase for the DLL to generate the ADC
clock. The 5-bit value adjusts the sampling phase in 32 steps
across one pixel time. Each step represents an 11.25° shift in
sampling phase. The power-up default is 16.
INPUT GAIN
The AD9984A can accommodate input signals with a full-scale
range between 0.5 V and 1.0 V p-p. Setting the red, green, or
blue channel gain to 511 corresponds to an input range of 1.0 V.
A red, green, or blue channel gain of 0 establishes an input range of
0.5 V. Note that increasing gain results in the picture having less
contrast (the input signal uses fewer available converter codes).
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