參數(shù)資料
型號(hào)： AD9984AKCPZ-170
廠商： Analog Devices Inc
文件頁數(shù)： 19/44頁
文件大?。?/td> 0K
描述： IC DISPLAY 10BIT 170MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 接口
應(yīng)用： 顯示器，處理，電視
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
AD9984A
Rev. 0 | Page 26 of 44
Hex
Address
Read/Write,
Read Only
Bits
Default
Value
Register Name
Description
3
**** 0***
Red Clamp Select.
0 = Clamp the red channel to ground.
1 = Clamp the red channel to midscale.
2
**** *0**
Green Clamp Select.
0 = Clamp the green channel to ground.
1 = Clamp the green channel to midscale.
1
**** **0*
Blue Clamp Select.
0 = Clamp the blue channel to ground.
1 = Clamp the blue channel to midscale.
0
**** ***0
Must be set to 0 for proper operation.
0x19
R/W
7:0
0000 1000
Clamp Placement
Places the clamp signal an integer number of clock periods after the
trailing edge of the Hsync signal.
0x1A
R/W
7:0
0010 0000
Clamp Duration
Number of clock periods that the clamp signal is actively clamping.
0x1B
R/W
7
0*** ****
Clamp and Offset
Clamp Polarity Override.
0 = The chip selects the clamp polarity.
1 = The polarity of the clamp signal is set by Reg. 0x1B, Bit 6.
6
*1** ****
Clamp Polarity. This bit is used only if Reg. 0x1B, Bit 7 is set to 1.
0 = Clamp polarity is negative.
1 = Clamp polarity is positive.
5
**0* ****
Auto-Offset Enable.
0 = Auto-offset is disabled.
1 = Auto-offset is enabled (offsets become the desired clamp code).
4:3
***1 1***
Auto-Offset Update Frequency. This selects how often the auto-
offset circuit operates.
00 = Every 3 clamps.
01 = Every 48 clamps.
10 = Every 192 clamps.
11 = Every 3 Vsync periods.
2:0
**** *011
Must be written to default (011) for proper operation.
0x1C
R/W
7:0
1111 1111
Test Register 0
Must be set to 0xFF for proper operation.
0x1D
R/W
7:3
0111 1***
SOG Control
SOG Slicer Comparator Threshold. Sets the voltage level of SOG slicer’s
comparator.
2
**** *0**
SOGOUT Polarity. Sets the polarity of the signal on the SOGOUT pin.
0 = SOGOUT polarity is negative.
1 = SOGOUT polarity is positive.
1:0
**** **00
SOGOUT Select.
00 = Raw SOGINx.
01 = Raw HSYNCx.
10 = Regenerated Hsync from sync filter.
11 = Filtered Hsync from sync filter.
0x1E
R/W
7
*** ****
Input and Power
Control
Channel Select Override.
0 = The chip determines which input channels to use.
1 = The input channel selection is determined by Reg. 0x1E, Bit 6.
6
*0** ****
Channel Select. This is used only if Reg. 0x1E, Bit 7 is set to 1, or if
syncs are present on both channels.
0 = Channel 0 syncs and data are selected.
1 = Channel 1 syncs and data are selected.
5
**1* ****
Programmable Bandwidth.
0 = Low analog input bandwidth (~7 MHz).
1 = High analog input bandwidth (~300 MHz).
4
***1 ****
Power-Down Control Select.
0 = Manual power-down control.
1 = Auto power-down control.
3
**** 0***
Power-Down.
0 = Normal operation.
1 = Power-down.
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